A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /spl mu/m CMOS process

A 300 MHz, 1 Mb SRAM with 5.4 ns access in 3.3 V, 0.5 /spl mu/m CMOS uses self-timed and self-resetting circuits. A dual-clock, flow-through read protocol optimizes data window control and a 750 ps setup-and-hold window for all input signals is achieved through floorplanning, receiver design and localized input-signal registering. The SRAM interfaces with high-speed transceiver logic (HSTL) levels through high-speed, noise-tolerant receivers. Programmable impedance output drivers for HSTL interfaces match transmission line impedance to within 10% tolerances over process, voltage and temperature variations.