H. Partovi, R. Burd, Udin Salim, F. Weber, Luigi DiGregorio, D. Draper
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引用次数: 421
Abstract
This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent latching structures for static logic, dynamic domino and self-resetting logic.