S. Atsumi, A. Umezawa, M. Kuriyama, H. Banba, N. Ohtsuka, N. Tomita, Y. Iyama, T. Miyaba, R. Sudoh, E. Kamiya, M. Tanimoto, Y. Hiura, Y. Araki, E. Sakagami, N. Arai, S. Mori
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A 3.3 V-only 16 Mb flash memory with row-decoding scheme
A 3.3 V only 16 M flash memory with a row decoding scheme is fabricated in 0.4 /spl mu/m double-well double-metal CMOS. Negative-gate-biased erase enables 3.3 V-only operation, and a double-word-line structure with second aluminum minimizes word-line delay. Row redundancy with self-convergence improves yield. Quasi-differential sensing with address transition detection gives fast random access.
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