K. Furumochi, H. Shimizu, M. Fujita, T. Akita, T. Izawa, M. Katsube, K. Aoyama, S. Kawamura
{"title":"用于片上缓存的500 MHz 288 kb CMOS SRAM宏","authors":"K. Furumochi, H. Shimizu, M. Fujita, T. Akita, T. Izawa, M. Katsube, K. Aoyama, S. Kawamura","doi":"10.1109/ISSCC.1996.488551","DOIUrl":null,"url":null,"abstract":"A 288 kb (4 kw by 72 b) embedded SRAM macro operates at 500 MHz. A modular design using a double-stage clock generator achieves the word-bit size flexibility required for embedded SRAM. This macro is intended to be used as an on-chip cache for high-speed CPUs.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"252 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A 500 MHz 288 kb CMOS SRAM macro for on-chip cache\",\"authors\":\"K. Furumochi, H. Shimizu, M. Fujita, T. Akita, T. Izawa, M. Katsube, K. Aoyama, S. Kawamura\",\"doi\":\"10.1109/ISSCC.1996.488551\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 288 kb (4 kw by 72 b) embedded SRAM macro operates at 500 MHz. A modular design using a double-stage clock generator achieves the word-bit size flexibility required for embedded SRAM. This macro is intended to be used as an on-chip cache for high-speed CPUs.\",\"PeriodicalId\":162539,\"journal\":{\"name\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"volume\":\"252 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1996.488551\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488551","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 500 MHz 288 kb CMOS SRAM macro for on-chip cache
A 288 kb (4 kw by 72 b) embedded SRAM macro operates at 500 MHz. A modular design using a double-stage clock generator achieves the word-bit size flexibility required for embedded SRAM. This macro is intended to be used as an on-chip cache for high-speed CPUs.
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