A 200M sample/s 6b flash ADC in 0.6 /spl mu/m CMOS

Abstract

This 6b flash analog-to-digital converter (ADC) performs the sampling function in a partial-response, maximum-likelihood disk drive read channel. The read channel must process signals with spectral content extending up to half the sampling rate. This requires an ADC with better than 5 effective bits at Nyquist, accomplished here using a full-flash architecture capable of sampling at 200 MHz. To meet cost objectives, the read channel is on 0.6 /spl mu/m single-poly CMOS, where the ADC achieves performance previously seen only on bipolar or BiCMOS processes.