A 56-entry instruction reorder buffer

N.B. Gaddis, J. R. Butler, A. Kumar, W. J. Queen
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引用次数: 21

Abstract

A speculative execution high-end PA-RISC CPU has two 28-entry out-of-order instruction reorder buffers (IRBs), one for alu/floating point operations and one for memory operations. The IRBs are capable of inserting any combination of four instructions per cycle. Each cycle, the IRBs launch up to four instructions for execution, two from the ALU IRB and two from the MEM IRB. Up to four instructions (two from each IRB) retire each cycle. The insert, launch and retire mechanisms of this out-of-order machine contain 850 k transistors in 52.6 mm/sup 2/.
一个包含56个条目的指令重排序缓冲区
一个推测执行的高端PA-RISC CPU有两个28个输入的乱序指令重排序缓冲区(irb),一个用于u/浮点操作,一个用于内存操作。irb能够在每个周期插入四个指令的任意组合。每个周期,IRB最多启动四个指令执行,两个来自ALU IRB,两个来自MEM IRB。每个周期最多有四条指令(每个IRB两条)退出。这台无序机器的插入、发射和退出机构包含850k晶体管,尺寸为52.6 mm/sup /。
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