Bit-line clamped sensing multiplex and accurate high-voltage generator for 0.25 /spl mu/m flash memories

T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume, K. Kimura
{"title":"Bit-line clamped sensing multiplex and accurate high-voltage generator for 0.25 /spl mu/m flash memories","authors":"T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume, K. Kimura","doi":"10.1109/ISSCC.1996.488504","DOIUrl":null,"url":null,"abstract":"A 105.9 mm/sup 2/ 128 Mb experimental chip using 0.25 /spl mu/m technology demonstrates the feasibility of circuits that take advantage of the potential scalability of flash memory cells and an accurate internal voltage generator that operates at 2.5 V Vcc: (1) a layout-pitch-relaxing bit-line clamped sensing multiplex and intermittent-burst data transfer (four phases with 500 ns/20 ns) for a 3F (F=feature size) pitch, and (2) a 5 /spl mu/A dynamic band-gap generator under a boosted voltage using triple-well bipolar transistors and a voltage doubler charge pump, for accurate 10 to 20 V generation.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488504","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

Abstract

A 105.9 mm/sup 2/ 128 Mb experimental chip using 0.25 /spl mu/m technology demonstrates the feasibility of circuits that take advantage of the potential scalability of flash memory cells and an accurate internal voltage generator that operates at 2.5 V Vcc: (1) a layout-pitch-relaxing bit-line clamped sensing multiplex and intermittent-burst data transfer (four phases with 500 ns/20 ns) for a 3F (F=feature size) pitch, and (2) a 5 /spl mu/A dynamic band-gap generator under a boosted voltage using triple-well bipolar transistors and a voltage doubler charge pump, for accurate 10 to 20 V generation.
位线钳位感测多路复用和精确的高压发生器,用于0.25 /spl mu/m闪存
采用0.25 /spl mu/m技术的105.9 mm/sup 2/ 128 Mb实验芯片证明了电路的可行性,该电路利用了闪存单元的潜在可扩展性和工作在2.5 V Vcc的精确内部电压发生器。(1) 3F (F=特征尺寸)节距下的布局-节距轻松位线钳位感测复用和间歇突发数据传输(四相,500 ns/20 ns);(2)在升压下的5 /spl mu/ a动态带隙发生器,采用三孔双极晶体管和倍压电荷泵,可精确产生10至20 V。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信