Monolithic low-power 16 b 1 MSample/s self-calibrating pipeline ADC

M. Mayes, S. Chin
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引用次数: 10

Abstract

Pipelined architectures enable the implementation of high-speed, high-resolution, low-power analog-to-digital converters (ADCs). Concurrent processing of analog signals results in power and/or speed advantages over flash and multistep ADC architectures. While self-calibration techniques reduce the effects of component mismatches, the digital crosstalk due to correction circuitry can degrade the noise and linearity performance of the overall converter. Previous pipeline ADCs achieve high speed and high resolution, but with the digital circuitry off chip. This 16 b 1 MSample/s pipeline ADC with on-chip digital correction circuitry operates on a single SV analog supply. Problems due to digital crosstalk and solutions reducing its effects are presented. Reduction of integral non-linearity (INL) errors due to capacitor voltage coefficient are discussed.
单片低功耗16b1msample /s自校准流水线ADC
流水线架构能够实现高速、高分辨率、低功耗的模数转换器(adc)。与闪存和多步ADC架构相比,模拟信号的并发处理具有功率和/或速度优势。虽然自校准技术减少了元件不匹配的影响,但由于校正电路引起的数字串扰会降低整个转换器的噪声和线性性能。以前的流水线adc实现了高速和高分辨率,但采用了片外数字电路。这款16b1msample /s流水线ADC带有片上数字校正电路,在单SV模拟电源上工作。提出了数字串扰产生的问题及降低其影响的方法。讨论了由电容电压系数引起的积分非线性误差的减小。
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