Monolithic low-power 16 b 1 MSample/s self-calibrating pipeline ADC

Abstract

Pipelined architectures enable the implementation of high-speed, high-resolution, low-power analog-to-digital converters (ADCs). Concurrent processing of analog signals results in power and/or speed advantages over flash and multistep ADC architectures. While self-calibration techniques reduce the effects of component mismatches, the digital crosstalk due to correction circuitry can degrade the noise and linearity performance of the overall converter. Previous pipeline ADCs achieve high speed and high resolution, but with the digital circuitry off chip. This 16 b 1 MSample/s pipeline ADC with on-chip digital correction circuitry operates on a single SV analog supply. Problems due to digital crosstalk and solutions reducing its effects are presented. Reduction of integral non-linearity (INL) errors due to capacitor voltage coefficient are discussed.