A 143-360 Mb/s auto-rate selecting data-retimer chip for serial-digital video signals

Abstract

Current serial digital video retimers have two limitations: (1) manufacturers are required to incorporate PCB adjustments for center frequency at each rate, and (2) auto rate selection (ARS) uses complex circuitry unnecessary for purely signal-routing applications. This circuitry, which relies on the successful detection of a de-scrambled 30 b word, operates at the clock rate and increases power dissipation. The retimer described here addresses these problems by (1) wafer trim to eliminate PCB tweaks, and (2) a simplified implementation of ARS.