{"title":"基于闪存技术的1mb 5晶体管/位非易失性CAM","authors":"T. Miwa, H. Yamada, Y. Hirota, T. Satoh, H. Hara","doi":"10.1109/ISSCC.1996.488505","DOIUrl":null,"url":null,"abstract":"A 1 Mb content-addressable memory LSI based on flash technologies (flash CAM) has memory cells consisting of a pair of flash memory cell transistors. 10.34 /spl mu/m/sup 2/ cell and 42.9mm/sup 2/ die are attained with 0.8 /spl mu/m design rules. The flash CAM can be searched for masked binary data. Read access time and search access time are 115 ns and 145 ns, respectively, with a 5 V supply voltage. Power dissipation is 200 mW at 3.3 MHz. The flash CAM cell consists of two floating-gate transistors. This structure is in strong contrast to the comparator-added-storage structure of 17-transistor SRAM-based cells or five-transistor two-capacitor of DRAM-based cells. In addition to non-volatility, flash CAMs also feature on-board programmable/erasable memory.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 1 Mb 5-transistor/bit non-volatile CAM based on flash-memory technologies\",\"authors\":\"T. Miwa, H. Yamada, Y. Hirota, T. Satoh, H. Hara\",\"doi\":\"10.1109/ISSCC.1996.488505\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1 Mb content-addressable memory LSI based on flash technologies (flash CAM) has memory cells consisting of a pair of flash memory cell transistors. 10.34 /spl mu/m/sup 2/ cell and 42.9mm/sup 2/ die are attained with 0.8 /spl mu/m design rules. The flash CAM can be searched for masked binary data. Read access time and search access time are 115 ns and 145 ns, respectively, with a 5 V supply voltage. Power dissipation is 200 mW at 3.3 MHz. The flash CAM cell consists of two floating-gate transistors. This structure is in strong contrast to the comparator-added-storage structure of 17-transistor SRAM-based cells or five-transistor two-capacitor of DRAM-based cells. In addition to non-volatility, flash CAMs also feature on-board programmable/erasable memory.\",\"PeriodicalId\":162539,\"journal\":{\"name\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1996.488505\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488505","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1 Mb 5-transistor/bit non-volatile CAM based on flash-memory technologies
A 1 Mb content-addressable memory LSI based on flash technologies (flash CAM) has memory cells consisting of a pair of flash memory cell transistors. 10.34 /spl mu/m/sup 2/ cell and 42.9mm/sup 2/ die are attained with 0.8 /spl mu/m design rules. The flash CAM can be searched for masked binary data. Read access time and search access time are 115 ns and 145 ns, respectively, with a 5 V supply voltage. Power dissipation is 200 mW at 3.3 MHz. The flash CAM cell consists of two floating-gate transistors. This structure is in strong contrast to the comparator-added-storage structure of 17-transistor SRAM-based cells or five-transistor two-capacitor of DRAM-based cells. In addition to non-volatility, flash CAMs also feature on-board programmable/erasable memory.