T. Takayanagi, K. Nogami, F. Hatori, N. Hatanaka, M. Takahashi, M. Ichida, S. Kitabayashi, T. Higashi, M. Klein, J. Thomson, R. Carpenter, R. Donthi, D. Renfrow, J. Zheng, L. Tinkey, B. Maness, J. Battle, S. Purcell, T. Sakurai
{"title":"350 MHz time-multiplexed 8-port SRAM and word size variable multiplier for multimedia DSP","authors":"T. Takayanagi, K. Nogami, F. Hatori, N. Hatanaka, M. Takahashi, M. Ichida, S. Kitabayashi, T. Higashi, M. Klein, J. Thomson, R. Carpenter, R. Donthi, D. Renfrow, J. Zheng, L. Tinkey, B. Maness, J. Battle, S. Purcell, T. Sakurai","doi":"10.1109/ISSCC.1996.488548","DOIUrl":null,"url":null,"abstract":"A multimedia DSP optimized for digital audio/video applications provides simple flexible cost-effective solution capable of GUI acceleration, MPEG2 decoding, real-time MPEG1 encoding, personal video conferencing, 28.8 kbps fax/modem, and audio/sound functions. The main frequency of the chip is 62.5 MHz and the supply voltage is 3.3 V. The chip is fabricated in 0.5 /spl mu/m triple-metal CMOS, occupies 12.8/spl times/14.0 mm/sup 2/ and is mounted in a 240 QFP package with a heat-spreader. The chip integrates high-performance custom macro blocks: an interface for Rambus DRAMs (RAC), a 37 kb time-multiplexed 8-ported SRAM, 72 b scalable datapath and single oxide 3 V/5 V I/O. The focus here is the SRAM and word-size-variable multiplier.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488548","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
A multimedia DSP optimized for digital audio/video applications provides simple flexible cost-effective solution capable of GUI acceleration, MPEG2 decoding, real-time MPEG1 encoding, personal video conferencing, 28.8 kbps fax/modem, and audio/sound functions. The main frequency of the chip is 62.5 MHz and the supply voltage is 3.3 V. The chip is fabricated in 0.5 /spl mu/m triple-metal CMOS, occupies 12.8/spl times/14.0 mm/sup 2/ and is mounted in a 240 QFP package with a heat-spreader. The chip integrates high-performance custom macro blocks: an interface for Rambus DRAMs (RAC), a 37 kb time-multiplexed 8-ported SRAM, 72 b scalable datapath and single oxide 3 V/5 V I/O. The focus here is the SRAM and word-size-variable multiplier.