一个200mb /s的模拟DFE读通道

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI:10.1109/ISSCC.1996.488519

N. Sands, M. Hauser, G. Liang, G. Groenewold, S. Lam, Chao-Ho Lin, J. Kuklewicz, L. Lang, R. Dakshinamurthy

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引用次数: 24

摘要

一个200mb /s的读通道IC实现了一个增强的决策反馈均衡器(DFE)，结合了连续和离散时间模拟和数字信号处理。该设计采用20 GHz的峰值-f/sub / T/ BiCMOS工艺，工作电压为5 V，功耗约为700 mW。所有相关功能包括:位检测，RLL编码器/解码器，伺服解调和写入预补偿。数据速率范围为64200mb /s，标准化记录密度为1.8-2.4。

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A 200 Mb/s analog DFE read channel

A 200 Mb/s read-channel IC realizes an enhanced decision-feedback equalizer (DFE) with a combination of continuous and discrete time analog and digital signal processing. The design uses a 20 GHz peak-f/sub T/, BiCMOS process operating at 5 V, with a power consumption of approximately 700 mW. All associated functions are included: bit detection, RLL encoder/decoder, servo demodulation, and write precompensation. Data rate range is 64200 Mb/s at a normalized recording density of 1.8-2.4.

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来源期刊

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

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