200mhz 256kb二级缓存，数据带宽1.6 GB/s

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI:10.1109/ISSCC.1996.488552

D. DiMarco, M. Balmer, C. Freeman, K. Hose, J.L. Miller, E. Riggs

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引用次数: 4

摘要

处理器性能的改进产生了紧耦合、高带宽的二级缓存，这是处理器性能的关键。本文介绍了一种256 kB、4路集关联的微处理器配套缓存SRAM。高速是通过将处理器和缓存保持在相同的2芯片模块中以及通过专用72b数据总线进行通信来实现的。电源电压为3.3 V，最大功率为3.8 W，在150 MHz，假设背靠背读取。BiCMOS工艺具有4级金属和0.4 /spl mu/m Leff。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 200 MHz 256 kB second level cache with 1.6 GB/s data bandwidth

Improvements in processor performance have given rise to tightly-coupled, high-bandwidth second-level caches that are key to processor performance. This paper describes a 256 kB, 4-way set-associative companion cache SRAM to a microprocessor. High speed is achieved by keeping the processor and cache in the same 2-chip module and by communicating over a private 72 b data bus. Supply voltage is 3.3 V and maximum power is 3.8 W at 150 MHz, assuming back-to-back reads. The BiCMOS process features 4-level metal and 0.4 /spl mu/m Leff.

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来源期刊

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

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