一种用于串行数字视频信号的143- 360mb /s自动选择数据定时器芯片

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI:10.1109/ISSCC.1996.488568

D. Potson, A. Buchholz

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引用次数: 7

摘要

目前的串行数字视频计时器有两个限制:(1)制造商需要在每个速率下结合PCB调整中心频率，(2)自动速率选择(ARS)使用复杂的电路，这对于纯粹的信号路由应用来说是不必要的。这种电路依赖于成功检测到一个解码的30b字，以时钟速率工作，并增加了功耗。这里描述的计时器通过(1)晶圆修剪来消除PCB调整，以及(2)ARS的简化实现来解决这些问题。

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A 143-360 Mb/s auto-rate selecting data-retimer chip for serial-digital video signals

Current serial digital video retimers have two limitations: (1) manufacturers are required to incorporate PCB adjustments for center frequency at each rate, and (2) auto rate selection (ARS) uses complex circuitry unnecessary for purely signal-routing applications. This circuitry, which relies on the successful detection of a de-scrambled 30 b word, operates at the clock rate and increases power dissipation. The retimer described here addresses these problems by (1) wafer trim to eliminate PCB tweaks, and (2) a simplified implementation of ARS.

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来源期刊

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

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