亚纳秒0.5 /spl mu/m 64b加法器设计

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI:10.1109/ISSCC.1996.488718

S. Naffziger

{"title":"亚纳秒0.5 /spl mu/m 64b加法器设计","authors":"S. Naffziger","doi":"10.1109/ISSCC.1996.488718","DOIUrl":null,"url":null,"abstract":"A sub-nanosecond 64 b adder in 0.5 /spl mu/m CMOS forms the basis for the integer and floating point execution units. Integrating dual-rail dynamic CMOS and use of Ling's equations, the adder is composed of 7k FETs in 0.246 mm/sup 2/ and performs a full 64 b add, operands to result in <1 ns (7 fanout of 4 inverter delays) under nominal conditions.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"41","resultStr":"{\"title\":\"A sub-nanosecond 0.5 /spl mu/m 64 b adder design\",\"authors\":\"S. Naffziger\",\"doi\":\"10.1109/ISSCC.1996.488718\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A sub-nanosecond 64 b adder in 0.5 /spl mu/m CMOS forms the basis for the integer and floating point execution units. Integrating dual-rail dynamic CMOS and use of Ling's equations, the adder is composed of 7k FETs in 0.246 mm/sup 2/ and performs a full 64 b add, operands to result in <1 ns (7 fanout of 4 inverter delays) under nominal conditions.\",\"PeriodicalId\":162539,\"journal\":{\"name\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"41\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1996.488718\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488718","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 41

摘要

0.5 /spl mu/m CMOS中的亚纳秒64 b加法器构成了整数和浮点执行单元的基础。该加法器集成了双轨动态CMOS并使用Ling方程，由7k fet组成，速度为0.246 mm/sup 2/，在标称条件下执行完整的64b加操作数，导致< 1ns(4个逆变器延迟中的7个风扇输出)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A sub-nanosecond 0.5 /spl mu/m 64 b adder design

A sub-nanosecond 64 b adder in 0.5 /spl mu/m CMOS forms the basis for the integer and floating point execution units. Integrating dual-rail dynamic CMOS and use of Ling's equations, the adder is composed of 7k FETs in 0.246 mm/sup 2/ and performs a full 64 b add, operands to result in <1 ns (7 fanout of 4 inverter delays) under nominal conditions.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

自引率

0.00%

发文量