G. Giacalone, R. Busch, F. Creed, A. Davidovich, S. Divakaruni, C. Drake, C. Ematrudo, J. Fifield, M. Hodges, W. Howell, P. Jenkins, M. Kozyrczak, C. Miller, T. Obremski, C. Reed, G. Rohrbaugh, M. Vincent, T. von Reyn, J. Zimmerman
{"title":"1mb, 100mhz集成L2缓存存储器，128b接口和ECC保护","authors":"G. Giacalone, R. Busch, F. Creed, A. Davidovich, S. Divakaruni, C. Drake, C. Ematrudo, J. Fifield, M. Hodges, W. Howell, P. Jenkins, M. Kozyrczak, C. Miller, T. Obremski, C. Reed, G. Rohrbaugh, M. Vincent, T. von Reyn, J. Zimmerman","doi":"10.1109/ISSCC.1996.488721","DOIUrl":null,"url":null,"abstract":"Several cache-DRAMs have been reported, but all require multiple chips to implement an L2 cache system. The advent of 20 ns, 16 Mb DRAM technology has made a high-speed single-chip 1MB cache possible, replacing multiple SRAM and logic modules, saving board space and reducing power. Multichip-module (MCM) packaging further optimizes the electrical characteristics of the processor-cache connection. An in-line level-2 1 MB cache chip that has DRAM density contains high-speed SRAM and MCM technology.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"A 1 MB, 100 MHz integrated L2 cache memory with 128b interface and ECC protection\",\"authors\":\"G. Giacalone, R. Busch, F. Creed, A. Davidovich, S. Divakaruni, C. Drake, C. Ematrudo, J. Fifield, M. Hodges, W. Howell, P. Jenkins, M. Kozyrczak, C. Miller, T. Obremski, C. Reed, G. Rohrbaugh, M. Vincent, T. von Reyn, J. Zimmerman\",\"doi\":\"10.1109/ISSCC.1996.488721\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Several cache-DRAMs have been reported, but all require multiple chips to implement an L2 cache system. The advent of 20 ns, 16 Mb DRAM technology has made a high-speed single-chip 1MB cache possible, replacing multiple SRAM and logic modules, saving board space and reducing power. Multichip-module (MCM) packaging further optimizes the electrical characteristics of the processor-cache connection. An in-line level-2 1 MB cache chip that has DRAM density contains high-speed SRAM and MCM technology.\",\"PeriodicalId\":162539,\"journal\":{\"name\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1996.488721\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488721","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1 MB, 100 MHz integrated L2 cache memory with 128b interface and ECC protection
Several cache-DRAMs have been reported, but all require multiple chips to implement an L2 cache system. The advent of 20 ns, 16 Mb DRAM technology has made a high-speed single-chip 1MB cache possible, replacing multiple SRAM and logic modules, saving board space and reducing power. Multichip-module (MCM) packaging further optimizes the electrical characteristics of the processor-cache connection. An in-line level-2 1 MB cache chip that has DRAM density contains high-speed SRAM and MCM technology.
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