Zhi-Gong Wang, M. Berroth, A. Thiede, M. Rieger-Motzer, P. Hofmann, A. Hulsmann, K. Kohler, B. Raynor, J. Schneider, D. Briggmann
{"title":"采用0.3 /spl mu/m HEMTs的全平衡窄带再生分频器实现10gb /s和20gb /s时钟恢复的电路技术","authors":"Zhi-Gong Wang, M. Berroth, A. Thiede, M. Rieger-Motzer, P. Hofmann, A. Hulsmann, K. Kohler, B. Raynor, J. Schneider, D. Briggmann","doi":"10.1109/ISSCC.1996.488572","DOIUrl":null,"url":null,"abstract":"The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes. At 10 Gb/s input data, the tank circuit of the preprocessor resonates at the second harmonic of the clock frequency. This mode can be used for 10 Gb/s direct data decision. At 20 Gb/s the tank circuit resonates at the fundamental frequency of the clock signal. This mode is optimal for a 20 Gb/s parallel data decision.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Circuit techniques for 10 and 20 Gb/s clock recovery using a fully balanced narrowband regenerative frequency divider with 0.3 /spl mu/m HEMTs [SDH/SONET]\",\"authors\":\"Zhi-Gong Wang, M. Berroth, A. Thiede, M. Rieger-Motzer, P. Hofmann, A. Hulsmann, K. Kohler, B. Raynor, J. Schneider, D. Briggmann\",\"doi\":\"10.1109/ISSCC.1996.488572\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes. At 10 Gb/s input data, the tank circuit of the preprocessor resonates at the second harmonic of the clock frequency. This mode can be used for 10 Gb/s direct data decision. At 20 Gb/s the tank circuit resonates at the fundamental frequency of the clock signal. This mode is optimal for a 20 Gb/s parallel data decision.\",\"PeriodicalId\":162539,\"journal\":{\"name\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1996.488572\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488572","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Circuit techniques for 10 and 20 Gb/s clock recovery using a fully balanced narrowband regenerative frequency divider with 0.3 /spl mu/m HEMTs [SDH/SONET]
The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes. At 10 Gb/s input data, the tank circuit of the preprocessor resonates at the second harmonic of the clock frequency. This mode can be used for 10 Gb/s direct data decision. At 20 Gb/s the tank circuit resonates at the fundamental frequency of the clock signal. This mode is optimal for a 20 Gb/s parallel data decision.