采用0.3 /spl mu/m HEMTs的全平衡窄带再生分频器实现10gb /s和20gb /s时钟恢复的电路技术

Zhi-Gong Wang, M. Berroth, A. Thiede, M. Rieger-Motzer, P. Hofmann, A. Hulsmann, K. Kohler, B. Raynor, J. Schneider, D. Briggmann
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引用次数: 4

摘要

该电路由四个子电路组成:预处理器、窄带再生分频器、移相放大器和限幅放大器。CR电路是完全平衡的,可以在两种模式下工作。当输入数据为10gb /s时,预处理器的槽电路以时钟频率的二次谐波谐振。此模式可用于10gb /s的直接数据决策。在20gb /s时,槽电路以时钟信号的基频谐振。这种模式对于20 Gb/s的并行数据决策是最优的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Circuit techniques for 10 and 20 Gb/s clock recovery using a fully balanced narrowband regenerative frequency divider with 0.3 /spl mu/m HEMTs [SDH/SONET]
The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes. At 10 Gb/s input data, the tank circuit of the preprocessor resonates at the second harmonic of the clock frequency. This mode can be used for 10 Gb/s direct data decision. At 20 Gb/s the tank circuit resonates at the fundamental frequency of the clock signal. This mode is optimal for a 20 Gb/s parallel data decision.
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