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2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer 一种用于CMOS宽带lna混频器的前馈噪声和失真消除技术
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008929
Chin-Fu Li, Shih-chieh Chou, C. Lai, Cuei-Ling Hsieh, J. Liu, Po-Chiun Huang
{"title":"A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer","authors":"Chin-Fu Li, Shih-chieh Chou, C. Lai, Cuei-Ling Hsieh, J. Liu, Po-Chiun Huang","doi":"10.1109/ASSCC.2014.7008929","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008929","url":null,"abstract":"This work presents a circuit technique for broadband LNA-mixer to improve the noise and distortion performance simultaneously. By introducing an auxiliary feedforward path that carries the LNA noise and third-order intermodulation distortion (IM3) with equal magnitude and opposite phase to mixer output, the overall noise and IM3 are reduced while the signal is enhanced. The power overhead is small compared to the conventional tradeoff between the power consumption and linearity performance. The test circuit using a 0.18μm CMOS process includes a shunt-feedback LNA and two cross-coupled active mixers. All the circuits consume 7.7 mA from a 1.8 V supply. The signal bandwidth is 2 GHz. At 900MHz the voltage gain and noise figure are 19 dB and 6.2 dB respectively. There is 2.7dB NF and 10.1dB IM3 improvements with only 15% power overhead.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122906121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET 基于动态阈值MOSFET的0.52 v 5.7 ghz低噪声分采样锁相环
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008936
S. Ikeda, Sang-yeop Lee, Hiroyuki Ito, N. Ishihara, K. Masu
{"title":"A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET","authors":"S. Ikeda, Sang-yeop Lee, Hiroyuki Ito, N. Ishihara, K. Masu","doi":"10.1109/ASSCC.2014.7008936","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008936","url":null,"abstract":"This paper proposes a low voltage sub-sampling PLL with dynamic threshold MOSFET (DTMOS). DTMOS switch can achieve higher on/off ratio, which prevents signal attenuation and leakage of a sub-sampling phase detector (SSPD) under low supply voltage. The proposed SSPD also employs double-balanced structure to suppress feedthrough in hold mode. DTMOS switches are also applied to a sub-sampling charge pump to reduce undesirable current leak. The proposed PLL was fabricated in a 65nm CMOS. Under the power supply of 0.52V, it shows a in-band phase noise of -98 dBc/Hz at 410 kHz, and the total power consumption of 1.72 mW at 5.71 GHz including frequency-locked loop.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122287748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS 用于100gbe的110mw 6位36gs /s交错SAR ADC，占地0.048 mm2，采用32nm SOI CMOS
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008867
L. Kull, Jan Plíva, T. Toifl, M. Schmatz, P. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. Andersen, Y. Leblebici
{"title":"A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS","authors":"L. Kull, Jan Plíva, T. Toifl, M. Schmatz, P. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. Andersen, Y. Leblebici","doi":"10.1109/ASSCC.2014.7008867","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008867","url":null,"abstract":"An area- and power-optimized asynchronous 32× interleaved SAR ADC achieving 36 GS/s at 110mW with 1V supply on the interleaver and 0.9 V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a power- and area-optimized binary SAR ADC, and an area-optimized clocked reference buffer with a tunable constant-current source. It achieves 32.6dB SNDR up to 3GHz and 31.6dB up to 18GHz input frequency and 98fJ/conversion-step with a core chip area of 340×140μm2 in 32nm SOI CMOS technology.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127725064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems 一种用于多核系统中最小化拥塞的4.9 mW神经网络任务调度程序
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008898
Youchang Kim, Gyeonghoon Kim, Injoon Hong, Donghyun Kim, H. Yoo
{"title":"A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems","authors":"Youchang Kim, Gyeonghoon Kim, Injoon Hong, Donghyun Kim, H. Yoo","doi":"10.1109/ASSCC.2014.7008898","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008898","url":null,"abstract":"A neural network task scheduler (NNTS) is proposed for the congestion-minimized network-on-chip in multi-core systems. The NNTS is composed of a near-optimal task assignment (NOTA) algorithm and a reconfigurable precision neural network accelerator (RP-NNA). The NOTA adopting a neural network is proposed to predict and avoid the network congestion intelligently. And the RP-NNA is implemented to improve the throughput of NOTA with dynamically adjustable precision. In the case that the NNTS is integrated into a NoC-based multi-core SoC for the augmented reality applications, 79.2% prediction accuracy of NoC communication pattern is achieved and the overall latency is reduced by 24.4%. As a result, the RP-NNA consumes only 4.9 mW and improves the energy efficiency of system by 22.7%.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131350170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI 超低功耗射频收发器，具有1.5 pj /bit的最大数字脉冲发射器和89.5 μ w的超再生RSSI
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008911
Hiroyuki Ito, Yoshihiro Yoneda, Taiki Ibe, Taisuke Hamada, N. Ishihara, K. Masu, S. Masui, Y. Momiyama
{"title":"An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI","authors":"Hiroyuki Ito, Yoshihiro Yoneda, Taiki Ibe, Taisuke Hamada, N. Ishihara, K. Masu, S. Masui, Y. Momiyama","doi":"10.1109/ASSCC.2014.7008911","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008911","url":null,"abstract":"This paper proposes an RF transceiver with a maximally-digital impulse transmitter (I-TX) and a superregenerative received-signal-strength-indicator (RSSI) circuit for wireless sensor network (WSN) application. Our I-TX enables strict bit-level duty cycling operation to achieve both ultra-low power consumption and superior energy-per-bit in kb/s to Mb/s range. The proposed RSSI for low-power localization and low-rate downlink measures input power by exploiting the phenomenon that the oscillation start-up time logarithmically accelerates as input power increases. The I-TX fabricated in a 65nm CMOS achieves energy-per-bit of 1.5 pJ/bit at 10 Mb/s which is better than previous works. The proposed RSSI with -85 dBm sensitivity consumes 89.5 μW with modest dynamic range and linearity.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130306092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS 10位320ms /s低成本SAR ADC，适用于20nm CMOS的IEEE 802.11ac应用
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008864
Chun-Cheng Liu
{"title":"A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS","authors":"Chun-Cheng Liu","doi":"10.1109/ASSCC.2014.7008864","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008864","url":null,"abstract":"This paper presents a low-cost SAR ADC design for IEEE 802.11ac applications. A binary-scaled recombination weighting method for SAR ADC is disclosed in this work. The proposed SAR ADC achieved 9.29 ENOB with an FOM of 6.8 fJ/conversion-step at 0.9 V and 160 MS/s, and achieved 9.20 ENOB with an FOM of 8.1 fJ/conversion-step at 1.0 V and 320 MS/s. The ADC core only occupies an area of 33 μm × 35 μm in 20-nm CMOS process.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114105296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 73
23Gbps 9.4pJ/bit 80/100GHz band CMOS transceiver with on-board antenna for short-range communication 23Gbps 9.4pJ/bit 80/100GHz波段CMOS收发器，带板载天线，用于短距离通信
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008888
K. Nakajima, Akihiro Maruyama, M. Kohtani, T. Sugiura, E. Otobe, Jaejin Lee, Shinhee Cho, Kyusub Kwak, Jeongseok Lee, T. Yoshimasu, M. Fujishima
{"title":"23Gbps 9.4pJ/bit 80/100GHz band CMOS transceiver with on-board antenna for short-range communication","authors":"K. Nakajima, Akihiro Maruyama, M. Kohtani, T. Sugiura, E. Otobe, Jaejin Lee, Shinhee Cho, Kyusub Kwak, Jeongseok Lee, T. Yoshimasu, M. Fujishima","doi":"10.1109/ASSCC.2014.7008888","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008888","url":null,"abstract":"Fully integrated 80GHz-band and 100GHz-band transceiver ICs using 65nm CMOS technology and on-board antennas for high-speed/short-range wireless communication system are demonstrated. To realize higher speed and lower power consumption than those of a 60GHz-band standard application such as IEEE802.11ad, a simple transceiver architecture with non-coherent amplitude shift keying (ASK) modulation method using W-band (75-110GHz) is adopted. The aggregate 80/100GHz-band transceiver modules demonstrate 23Gbps over 10mm wirelessly with power consumption of 216mW. The developed transceiver modules achieve the highest speed of wireless communications above 60GHz-band and show a potential for future applications of 100Gbps high-speed short-range communications.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121811619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Energy efficient computing in nanoscale CMOS: Challenges and opportunities 纳米级CMOS节能计算:挑战与机遇
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008875
V. De
{"title":"Energy efficient computing in nanoscale CMOS: Challenges and opportunities","authors":"V. De","doi":"10.1109/ASSCC.2014.7008875","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008875","url":null,"abstract":"Future computing systems spanning exascale supercomputers to wearable devices demand orders of magnitude improvements in energy efficiency while providing desired performance. The system-on-chip (SoC) designs need to span a wide range of performance and power across diverse platforms and workloads. The designs must achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS process while supporting a wide voltage-frequency operating range with minimal impact on die cost. Circuit and design technologies need to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121125669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Highly improved SNR differential sensing method using parallel operation signaling for touch screen application 采用并行操作信号的高改进信噪比差分传感方法在触摸屏上的应用
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008884
Sanghyun Heo, Hyunggun Ma, Jae Joon Kim, F. Bien
{"title":"Highly improved SNR differential sensing method using parallel operation signaling for touch screen application","authors":"Sanghyun Heo, Hyunggun Ma, Jae Joon Kim, F. Bien","doi":"10.1109/ASSCC.2014.7008884","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008884","url":null,"abstract":"In this paper, a continuous-time differential type multi-signal parallel driving architecture touch screen sensing circuit for projective capacitive type panel is presented. In order to further enhance the Signal-to-Noise Ratio (SNR), a new transmitter (TX) architecture is proposed with parallel signal processing algorithm. In this work, charge amplifiers with built-in band-pass filter are designed that filter out low frequency noise and common-mode noise simultaneously. Conventional approaches in continuous-time operation with band-pass filter suffer from a synchronization problem in the case of multi-signal parallel driving. In this work, a built-in delay calibration circuit is proposed that can align signal timing for TX signal and adjacent receiver (RX) sensing line. This proposed architecture enables multi-signal parallel driving in continuous-time operation for projective capacitive sensing circuits. The proposed work supports 16 × 8 mutual capacitive touch screen panel (TSP). TSP load is 12.5 kΩ and 40 pF with frame rate of 200 Hz and 58 dB SNR. Power dissipation is 46 mW.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121239206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A DC-46Gb/s 2:1 multiplexer and source-series terminated driver in 20nm CMOS technology 采用20nm CMOS技术的DC-46Gb/s 2:1多路复用器和源系列端接驱动器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008939
J. Jiang, S. Parikh, Mark Lionbarger, N. Nedovic, T. Yamamoto
{"title":"A DC-46Gb/s 2:1 multiplexer and source-series terminated driver in 20nm CMOS technology","authors":"J. Jiang, S. Parikh, Mark Lionbarger, N. Nedovic, T. Yamamoto","doi":"10.1109/ASSCC.2014.7008939","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008939","url":null,"abstract":"We present a 46Gb/s 2:1 multiplexer and a source series terminated full rate driver for high speed chip-to-chip communications. The multiplexer and the driver are implemented using the pseudo-differential static CMOS circuit. Transmitter driver uses the push-pull structure to produce a VDD peak-to-peak differential voltage swing. The circuit uses no current mode logic gates or large on-chip passive devices aside from series-connected on-chip resistor and the T-coil used to minimize the return loss. We confirmed the total jitter of about 7ps at 46Gb/s and eye opening of 0.605UI up to 50 Gb/s on the test circuit fabricated in 20nm CMOS technology. Measured power consumption is 38.7mW at 46Gb/s (0.84pJ/b power efficiency).","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125804339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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