A DC-46Gb/s 2:1 multiplexer and source-series terminated driver in 20nm CMOS technology

Abstract

We present a 46Gb/s 2:1 multiplexer and a source series terminated full rate driver for high speed chip-to-chip communications. The multiplexer and the driver are implemented using the pseudo-differential static CMOS circuit. Transmitter driver uses the push-pull structure to produce a VDD peak-to-peak differential voltage swing. The circuit uses no current mode logic gates or large on-chip passive devices aside from series-connected on-chip resistor and the T-coil used to minimize the return loss. We confirmed the total jitter of about 7ps at 46Gb/s and eye opening of 0.605UI up to 50 Gb/s on the test circuit fabricated in 20nm CMOS technology. Measured power consumption is 38.7mW at 46Gb/s (0.84pJ/b power efficiency).