发布求助
文献互助 智能选刊 最新文献

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

筛选
英文 中文
RF transconductor linearization technique robust to process, voltage and temperature variations 射频变换器线性化技术对工艺、电压和温度变化具有鲁棒性
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-11 DOI: 10.1109/ASSCC.2014.7008928
H. Kundur, E. Klumperink, B. Nauta, V. Srinivasan, Ali Kiaei
{"title":"RF transconductor linearization technique robust to process, voltage and temperature variations","authors":"H. Kundur, E. Klumperink, B. Nauta, V. Srinivasan, Ali Kiaei","doi":"10.1109/ASSCC.2014.7008928","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008928","url":null,"abstract":"A new reconfigurable linearized low noise transconductance amplifier (LNTA) design for a software-defined radio receiver is presented. The transconductor design aims at realizing high linearity at RF in a way that is robust for Process, Voltage and Temperature variations. It exploits resistive degeneration in combination with a floating battery by-pass circuit and replica biasing to improve IIP3 in a robust way. The LNTA with current domain mixer is implemented in a 45nm CMOS process. Compared to an inverter based LNTA with the same transconductance, it improves PIIP3 from 2 dBm to a robust PIIP3 of 8 dBm at the cost of 67% increase in power consumption.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124279859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An 83% peak efficiency and 1.07W/mm2 power density Single Inductor 4-Output DC-DC converter with Bang-Bang Zeroth-Order Control 峰值效率为83%，功率密度为1.07W/mm2，具有Bang-Bang零阶控制的单电感4输出DC-DC变换器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-10 DOI: 10.1109/ASSCC.2014.7008860
Dongmin Park, Tae-Hwang Kong, Sukhwan Choi, G. Cho
{"title":"An 83% peak efficiency and 1.07W/mm2 power density Single Inductor 4-Output DC-DC converter with Bang-Bang Zeroth-Order Control","authors":"Dongmin Park, Tae-Hwang Kong, Sukhwan Choi, G. Cho","doi":"10.1109/ASSCC.2014.7008860","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008860","url":null,"abstract":"This paper presents a new control scheme dubbed Bang-Bang Zeroth-Order Control (BBZOC) for Single Inductor Multiple Output (SIMO) buck converter. The main loop control utilizes a phase detector, charge pump, filter, and comparator. The SIMO buck converter with BBZOC simplifies the compensation design compared to conventional voltage mode control. This work is fabricated in 1P4M 0.35um BCD process and achieves 83% maximum efficiency with the rated output power of 1.04W. The maximum output power is 2.7W and the maximum power density is 1.07 W/mm2. Considering the difference in the process, this work represents the state of the art in the power density.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"33 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130994710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
0.2 V 8T SRAM with improved bitline sensing using column-based data randomization 使用基于列的数据随机化改进位线传感的0.2 V 8T SRAM
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008880
A. Do, Zhao Chuan Lee, Bo Wang, I. Chang, T. T. Kim
{"title":"0.2 V 8T SRAM with improved bitline sensing using column-based data randomization","authors":"A. Do, Zhao Chuan Lee, Bo Wang, I. Chang, T. T. Kim","doi":"10.1109/ASSCC.2014.7008880","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008880","url":null,"abstract":"8T SRAMs operating at sub-threshold supply voltages suffer from bit-line swing degradation when the data pattern of a column is dominated by `1' or `0'. Worst case scenarios happen when the accessed bit is different from the rest of the column. In this work, a simplified Linear Feedback Shift Register (LFSR) is used to shuffle input data so that distribution of “1” and “0” in each column is close to 50%. As a result, bit-line sensing margin is enhanced. In addition, a bitline boost biasing scheme is applied to further increase the bitline swing and the sensing window. A 16Kb test chips fabricated in a 65 nm CMOS technology demonstrates successful SRAM operation at 0.2 V, room temperate, having power consumption and access time of 0.7 μW and 2.5 μs, respectively.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115377676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput 具有240MB/s写入吞吐量和260MB/s读取吞吐量的UHS-II SD卡控制器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008852
K. Yasufuku, Naoto Oshiyama, Toshitada Saito, Y. Miyamoto, Yutaka Nakamura, R. Terauchi, A. Kondo, Takuma Aoyama, Masafumi Takahashi, Y. Oowaki, Ryoichi Bandai
{"title":"A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput","authors":"K. Yasufuku, Naoto Oshiyama, Toshitada Saito, Y. Miyamoto, Yutaka Nakamura, R. Terauchi, A. Kondo, Takuma Aoyama, Masafumi Takahashi, Y. Oowaki, Ryoichi Bandai","doi":"10.1109/ASSCC.2014.7008852","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008852","url":null,"abstract":"This paper presents a UHS-II SD card controller with 240MB/s write and 260MB/s read throughput. Two opposite direction IO lanes for down- and up-streams are quickly switched as single direction for double data rate, without adding extra IO pins. The proposed clock data recovery (CDR) logic can detect symbols within 20ns and minimizes this lane switching overhead. The developed SLVS-type driver that can reduce the common to differential return loss by 15dB is also introduced to improve the noise tolerance.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"232 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120861184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10μA on-chip electrochemical impedance spectroscopy system for wearables/implantables 用于可穿戴/植入式设备的10μA片上电化学阻抗谱系统
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008922
Jingren Gu, H. Yao, Keping Wang, B. Parviz, B. Otis
{"title":"A 10μA on-chip electrochemical impedance spectroscopy system for wearables/implantables","authors":"Jingren Gu, H. Yao, Keping Wang, B. Parviz, B. Otis","doi":"10.1109/ASSCC.2014.7008922","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008922","url":null,"abstract":"This work proposes a new time-domain integration method to realize Electrochemical Impedance Spectroscopy (EIS). Unlike traditional EIS systems which use a quadrature sinusoid stimulus, we propose a low-frequency, low-amplitude sinusoid stimulus, which is realized through a sinusoid DAC without the need for analog filter. The error caused by harmonic generation can be suppressed through integration in detection. The response current is sensed by a switched capacitor integrator with control synchronized with sinusoid DAC. The integration output is sampled and digitized by an 8-bit SAR ADC. The (1×1.1)mm2 prototype is fabricated in a 130nm CMOS process. It consumes 10μA from a 1.2V supply.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127110943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 0.1–5GHz flexible SDR receiver in 65nm CMOS 基于65nm CMOS的0.1-5GHz柔性SDR接收机
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008907
Xinwang Zhang, Yang Xu, Bingqiao Liu, Qian Yu, Siyang Han, Qiongbing Liu, Zehong Zhang, Yanqiang Gao, Zhihua Wang, B. Chi
{"title":"A 0.1–5GHz flexible SDR receiver in 65nm CMOS","authors":"Xinwang Zhang, Yang Xu, Bingqiao Liu, Qian Yu, Siyang Han, Qiongbing Liu, Zehong Zhang, Yanqiang Gao, Zhihua Wang, B. Chi","doi":"10.1109/ASSCC.2014.7008907","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008907","url":null,"abstract":"A 0.1-5GHz flexible software-defined radio (SDR) receiver is presented with three RF front-end paths (Main/Sub/HR paths). Main path and sub path can reject out-of-band blockers and harmonic interferences, and feature low NF and high linearity, respectively. Harmonic rejection (HR) path can effectively reject the harmonic interferences with simple calibration mechanism. Dual feedback LNA, class-AB Op-Amp with miller feed-forward compensation and quasi-floating gate (QFG) techniques, reconfigurable continuous-time (CT) low pass (LP) and complex band pass (CBP) sigma-delta ADC are proposed. This chip has been implemented in 65nm CMOS with 9.6-47.4mA current consumption from 1.2V voltage supply and a core chip area of 5.4mm2. The receiver main path achieves 3.8dB NF, +5dBm/+5dBm IB-IIP3/OB-IIP3 as well as +58dBm IIP2. The sub path achieves +10dBm/+18dBm IB-IIP3/OB-IIP3 as well as +61dBm IIP2. And it offers RF filtering with 10dB rejection at 10MHz offset. The HR path achieves +13dBm/+14dBm IB-IIP3/OB-IIP3 and >54/56dB 3rd/5th-order harmonic rejection with 30-40dB rejection improvement by calibration.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116059979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor 非对称锁频环(AFLL)用于28nm SPARC M6处理器的自适应时钟生成
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008938
Yifan YangGong, Sebastian Turullols, Daniel Woo, Chang-Yang Huang, King C. Yen, V. Krishnaswamy, K. Holdbrook, Jinuk Luke Shin
{"title":"Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor","authors":"Yifan YangGong, Sebastian Turullols, Daniel Woo, Chang-Yang Huang, King C. Yen, V. Krishnaswamy, K. Holdbrook, Jinuk Luke Shin","doi":"10.1109/ASSCC.2014.7008938","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008938","url":null,"abstract":"In order to minimize the impact of on-chip Ldi/dt noise on power and performance, Oracle's SPARC M6 processor features an Asymmetric Frequency Locked Loop (AFLL) that dynamically adjusts chip frequency. It achieves 15% improved noise immunity by reacting to the voltage noise asymmetrically through the use of a pair of DCO's that accurately track the response of critical paths. The AFLL is implemented in 28nm CMOS process in 0.045mm2 of area, dissipating 14mW, and reducing jitter by 50%.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116244721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS 40nm LP CMOS中0.3339 fj /bit/search高能效TCAM宏设计
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008877
Po-Tsang Huang, Shu-Lin Lai, C. Chuang, W. Hwang, Jason Huang, A. Hu, Paul-Sen Kan, Michael Jia, Kimi Lv, B. Zhang
{"title":"0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS","authors":"Po-Tsang Huang, Shu-Lin Lai, C. Chuang, W. Hwang, Jason Huang, A. Hu, Paul-Sen Kan, Michael Jia, Kimi Lv, B. Zhang","doi":"10.1109/ASSCC.2014.7008877","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008877","url":null,"abstract":"In this paper, a 256×40 energy-efficient ternary content addressable memory (TCAM) macro is designed and implemented in 40nm low power (LP) CMOS. Due to the thicker gate oxide in LP process, a 16T TCAM cell with p-type comparison circuits is proposed to increase the Ion/Ioff difference of the dynamic circuitry. To further improve energy efficiency, don't-care-based ripple search-lines/bit-lines are used to reduce both the switching activities and wire capacitance. Moreover, column-based data-aware power control is employed for leakage power reduction and write-ability improvements. The experimental results show a leakage power reduction of 28.9%, a search-line power reduction of 31.74% and an energy efficiency metric of the TCAM macro of 0.339 fJ/bit/search.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122705093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 2.5W tablet speaker delivering 3.2W pseudo high power by psychoacoustic model based adaptive power management system 基于心理声学模型的自适应电源管理系统，实现2.5W平板扬声器的3.2W伪大功率输出
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008900
Shin-Hao Chen, S. Peng, Ke-Horng Chen, Shin-Chi Lai, Sheng Kang, Kevin Cheng, Ying-Hsi Lin, Chen-Chih Huang, Chao-Cheng Lee
{"title":"A 2.5W tablet speaker delivering 3.2W pseudo high power by psychoacoustic model based adaptive power management system","authors":"Shin-Hao Chen, S. Peng, Ke-Horng Chen, Shin-Chi Lai, Sheng Kang, Kevin Cheng, Ying-Hsi Lin, Chen-Chih Huang, Chao-Cheng Lee","doi":"10.1109/ASSCC.2014.7008900","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008900","url":null,"abstract":"For a 2.5W speaker in tablets, the proposed adaptive power management (APM) system can deliver a pseudo high power of 3.2W with a ±4V supply because it suppresses 0.7W power on tones that may damage a 2.5W speaker and escape the notice of human ears. With z-domain digital signal processing (z-DSP) and psychoacoustic model, high efficient power management and high sound quality can be achieved simultaneously. Conventional automatic gain control (AGC) only has the ability of 0.32W power suppression. Moreover, suppressing power by conventional clipping technique increases total-harmonic-distortion (THD). In contrast, the proposed real-time dynamic loading impedance (RT-DLI) monitoring brings forward a way to solve the problem on speaker damage while keeping low THD during high sound pressure level (SPL). THD in the APM system is slightly higher than that of original sound 1.1dB, comparing to the disadvantage of 8.6dB increasing caused by conventional clipping technique.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129744178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 135-μW 0.46-mΩ/√Hz thoracic impedance variance monitor with square-wave current modulation 135 μ w 0.46-mΩ/√Hz方波电流调制胸廓阻抗变化监测仪
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008921
Chih-Chan Tu, Feng-Wen Lee, D. Yeih, Tsung-Hsien Lin
{"title":"A 135-μW 0.46-mΩ/√Hz thoracic impedance variance monitor with square-wave current modulation","authors":"Chih-Chan Tu, Feng-Wen Lee, D. Yeih, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2014.7008921","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008921","url":null,"abstract":"A low-power high-resolution thoracic impedance variance (TIV) monitoring circuit is presented. The TIV information is extracted by injecting a square-wave modulated current to the body. The resulted voltage is then demodulated by a proposed delayed-sampling technique. This proposed technique solves the gain-error issue occurred in prior square-wave modulated architectures. Furthermore, compared with sine-wave modulation, the proposed TIV monitoring circuit is more power efficient. Fabricated in a 0.18-μm CMOS, this chip draws 75 μA from a 1.8-V supply. The equivalent input-referred impedance noise density is only 0.46 mΩ/VHz.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121637404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信