2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献_第2页

A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process 26.5 Gb/s全数字时钟光接收机，采用65nm CMOS工艺实现数据恢复

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008870

Sang-Hyeok Chu, W. Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, D. Jeong

引用次数: 4

A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator 具有主要静态/部分动态可重构阵列加速器的4.5至13倍节能嵌入式微处理器

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008854

Itaru Hida, Dahoo Kim, T. Asai, M. Motomura

引用次数: 0

A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS 一个2 × 20 gb /s, 1.2 pj /bit, 40纳米CMOS时间交错光接收器

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008869

Shih-Hao Huang, Zheng-Hao Hong, Wei-Zen Chen

引用次数: 4

A power efficient frequency shaping neural recorder with automatic bandwidth adjustment 具有自动带宽调节功能的高效功率频率整形神经记录器

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008894

Jian Xu, Tong Wu, Zhi Yang

{"title":"A power efficient frequency shaping neural recorder with automatic bandwidth adjustment","authors":"Jian Xu, Tong Wu, Zhi Yang","doi":"10.1109/ASSCC.2014.7008894","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008894","url":null,"abstract":"This paper presents a frequency-shaping (FS) neural recorder with automatic bandwidth adjustment. The proposed recorder inherently attenuates electrode offset and motion artifacts, compresses neural data dynamic range by 4.5-bit, and achieves a 3 pF input impedance to better support chronic recording experiments. A major drawback of an FS recorder is larger input referred noise due to noise aliasing and reduced gain at low frequencies. In this work, we have proposed a multi-phase sampling and processing technique which can 10 times reduce the noise. In addition, a neural spike processor operating at a low duty cycle has been integrated, where the processing results are feedback to the analog frontend: when the channel contains no/little spike activities, the recorder bandwidth is automatically reduced to record local field potentials (LFPs) only. The bandwidth reduction enables substantial power saving for that channel (4 times in the current implementation). The bandwidth is then automatically restored back to 8 kHz once spikes are detected from the spiking probability map. A prototyping chip has been fabricated in a 0.13 μm CMOS process. When measured at a 80 kHz sampling clock and 1.0 V supply, the recorder achieves a 3 pF input capacitance, 2.2 μV input noise for recording spikes, and 15 μW/ch power for amplifiers, filters, multiplexer, analog-to-digital converter (ADC), and digital filters combined. Empirical studies on in-vivo recordings from monkeys show that over 70% of channels do not contain detectable spikes, suggesting an averaged recording power reduction by 50% to 7.5 μW/ch.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115616758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An 87×49 mutual capacitance touch sensing IC enabling 0.5 mm-diameter stylus signal detection at 240 Hz-reporting-rate with palm rejection 一种87×49互电容触摸传感IC，能够以240 hz的报告率检测0.5 mm直径的触控笔信号

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008899

S. Yoshida, M. Hamaguchi, T. Morishita, Shinji Shinjo, Akira Nagao, M. Miyamoto

{"title":"An 87×49 mutual capacitance touch sensing IC enabling 0.5 mm-diameter stylus signal detection at 240 Hz-reporting-rate with palm rejection","authors":"S. Yoshida, M. Hamaguchi, T. Morishita, Shinji Shinjo, Akira Nagao, M. Miyamoto","doi":"10.1109/ASSCC.2014.7008899","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008899","url":null,"abstract":"A touch sensing system capable of stylus input should have “palm rejection” function which allows the user to place one's palm on the surface of the touch sensor while writing with a stylus. In order to realize “palm rejection”, it is necessary to detect the small stylus while neglecting large signal from the palm. However this is not sufficient because small electrical noise injected through the palm into the touch sensor impedes stylus input signal in real use. This issue is because the injected noise propagates onto the touch sensor's sense channels which are capacitively-coupled with the palm and degrades the SNR of the stylus signal on the channels. A simple and effective technique to eliminate this issue is implemented in a newly developed 87×49 mutual capacitance touch sensing IC which is fabricated in an 85 nm CMOS technology. It achieves an SNR over 33 dB for a 0.5 mm-diameter stylus when a 10 Vp-p sinusoidal noise is injected to the stylus and the palm. Both the die area and the power consumption of a unit charge-to-voltage converter (CVC) designed for the IC are reduced to approximately 50% compared to those of the previous implementation [4]. In order not to report unwanted touches due to palm signals, a palm detection filter is implemented in the digital signal processor on the IC.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123917977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing 一种新型的2.4 ~ 3.6 GHz宽带次谐波注入锁相环，具有自适应对准注入定时

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008937

Zhao Zhang, Liyuan Liu, N. Wu

引用次数: 9

A current-mode buck converter with bandwidth reconfigurable for enhanced efficiency and improved load transient response 一种带宽可重构的电流型降压变换器，可提高效率和改善负载瞬态响应

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008862

Pai-Yi Wang, Li-Te Wu, T. Kuo

引用次数: 2

A 5.2mW IEEE 802.15.6 HBC standard compatible transceiver with power efficient delay-locked-loop based BPSK demodulator 一个5.2mW的IEEE 802.15.6 HBC标准兼容收发器，具有低功耗的基于延迟锁环的BPSK解调器

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008919

Hyunwoo Cho, Hyungwoo Lee, Joonsung Bae, H. Yoo

引用次数: 11

A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS 基于0.18μm CMOS的0.3V 10bit 7.3fJ/转换阶SAR ADC

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008926

C. Hsieh, Shen-Iuan Liu

引用次数: 15

A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers 频率可重构多标准65nm CMOS数字发射机与LTCC中间体

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008931

N. Kuo, Bonjern Yang, Chaoying Wu, Lingkai Kong, Angie Wang, M.T. Reiha, E. Alon, A. Niknejad, B. Nikolić

引用次数: 5