A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS

Abstract

A 0.3V 10-bit rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC) is realized in 0.18-μm CMOS process. While the supply is 0.3V, a double-boosted sampling switch and a supply-boosted time-domain comparator are proposed to decrease the on-resistance of the switches and improve the conversion time, respectively. To lower the power, differential dynamic switches are used to control the splitting capacitors of the digital-to-analog converter. This ADC achieves the SNDR of 54.57dB and the SFDR of 69.89dB, respectively. The power consumes 15.9nW at 5kS/s from a 0.3V supply. A figure-of-merit of 7.3fJ/conversion-step for this ADC is achieved.