{"title":"一个2 × 20 gb /s, 1.2 pj /bit, 40纳米CMOS时间交错光接收器","authors":"Shih-Hao Huang, Zheng-Hao Hong, Wei-Zen Chen","doi":"10.1109/ASSCC.2014.7008869","DOIUrl":null,"url":null,"abstract":"This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μApp at bit-error-rate of less than 10-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm2.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS\",\"authors\":\"Shih-Hao Huang, Zheng-Hao Hong, Wei-Zen Chen\",\"doi\":\"10.1109/ASSCC.2014.7008869\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μApp at bit-error-rate of less than 10-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm2.\",\"PeriodicalId\":161031,\"journal\":{\"name\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2014.7008869\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2014.7008869","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS
This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μApp at bit-error-rate of less than 10-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm2.
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