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2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications 用于移动医疗保健应用的0.65V 1.2mW 2.4GHz/400MHz双模相位调制器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008910
Yang Li, N. Xu, Yining Zhang, W. Rhee, Sanghoon Kang, Zhihua Wang
{"title":"A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications","authors":"Yang Li, N. Xu, Yining Zhang, W. Rhee, Sanghoon Kang, Zhihua Wang","doi":"10.1109/ASSCC.2014.7008910","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008910","url":null,"abstract":"A 0.65V 2.4GHz/400MHz digital-intensive phase modulator is implemented in 65nm CMOS. In ultra-low voltage design, the two-point modulator suffers a lot from the DCO nonlinearity. In this work, we employ a 2.4GHz semidigital fractional-N PLL with an FIR filter embedded 1-bit high-pass modulation to overcome the nonlinearity problem in the conventional two-point modulator. The 400MHz modulator performs an FIR-embedded OQPSK modulation to reduce the spectral regrowth in high frequencies. For compact area and low voltage design, an inverter based phase interpolator with a harmonic filtering technique is designed after generating multiphase signals directly from the 2.4GHz output. The 1Mb/s GFSK 2.4GHz and the 10Mb/s OQPSK 400MHz modulators consume 0.94mW and 1.2mW and achieve the EVM values of 5.7% and 6.4% respectively.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134615283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 10b 100kS/s SAR ADC with charge recycling switching method 一个10b 100kS/s的SAR ADC，带电荷循环切换方法
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008927
Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin
{"title":"A 10b 100kS/s SAR ADC with charge recycling switching method","authors":"Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin","doi":"10.1109/ASSCC.2014.7008927","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008927","url":null,"abstract":"This paper presents a low-voltage and energy-efficient 10b SAR ADC which manipulates charge recycling switching method for saving the switching energy. In additional, a window-based reconfigurable comparator is used to achieve fast comparison and small power dissipation. The proposed 10b SAR ADC operates at 100kS/s with 0.4V supply voltage in 90nm CMOS. The measurement results show that the prototype ADC achieve 55.37dB SNDR at Nyquist rate with only 107nW. The Figure-of-Merit (FoM) is 2.23fJ/conv.-step.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114476018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 44.9% PAE digitally-assisted linear power amplifier in 40 nm CMOS 40纳米CMOS数字辅助线性功率放大器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008932
Haoyu Qian, J. Silva-Martínez
{"title":"A 44.9% PAE digitally-assisted linear power amplifier in 40 nm CMOS","authors":"Haoyu Qian, J. Silva-Martínez","doi":"10.1109/ASSCC.2014.7008932","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008932","url":null,"abstract":"This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA segments are switched on and off according to signal power, i.e. the proposed scheme makes the PA power consumption correlate with the power of the input signal. Binary power gain variations due to segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the trade-off between efficiency and linearity by employing the digital predistortion technique. The PA is implemented in 40 nm CMOS process, it delivers a saturated output power of 35 dBm with 44.9% power-added efficiency (PAE) and linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at ±5 MHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is -35.8 dBc.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125062969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 3 Gb/s 64-QAM E-band direct-conversion transmitter in 40-nm CMOS 40nm CMOS的3gb /s 64-QAM e波段直接转换发射机
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008889
Dixian Zhao, P. Reynaert
{"title":"A 3 Gb/s 64-QAM E-band direct-conversion transmitter in 40-nm CMOS","authors":"Dixian Zhao, P. Reynaert","doi":"10.1109/ASSCC.2014.7008889","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008889","url":null,"abstract":"This paper describes a fully integrated E-band transmitter (TX) in 40-nm CMOS. Circuit, layout and calibration techniques are presented to suppress the LO feed-through (LOFT) and I/Q imbalance over both 71-76 and 81-86 GHz bands. A systematic design methodology is proposed for the millimeter-wave poly-phase filter (PPF) to achieve lowest I/Q imbalance with minimum EM simulations. The 40-nm E-band transmitter achieves a measured output power of 12 dBm and TX efficiency of 15% with about 15 GHz bandwidth. Measured from 3 chips, the transmitter features an un-calibrated I/Q imbalance of less than -30 dB from 62.5 to 85.5 GHz. The calibration circuits further reduce the I/Q imbalance by 3-5 dB and ensure the LOFT less than -30 dBc over more than 30 dB output dynamic range. The presented TX achieves 3-Gb/s 64-QAM across the complete E-band.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122573851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 0.43pJ/bit true random number generator 一个0.43pJ/bit的真随机数生成器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008853
Ting-Kuei Kuan, Yu-Hsuan Chiang, Shen-Iuan Liu
{"title":"A 0.43pJ/bit true random number generator","authors":"Ting-Kuei Kuan, Yu-Hsuan Chiang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2014.7008853","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008853","url":null,"abstract":"A small-area energy-efficient true random number generator (TRNG) is presented. This TRNG introduces a jitter signal generator to realize the noise pre-amplification, and utilizes a metastable latch to resolve the jitter edges. Moreover, to tolerate the process and environment variations, an offset calibration is employed to dynamically correct the bias of the probability of logic 0/1 in background. A prototype is fabricated in 40-nm CMOS technology. It occupies an area of 0.0014mm2 and consumes 214nW from a 0.8-V supply at a throughput of 500kbps. The proposed TRNG passes the NIST tests, and its calculated FOM is 0.43pJ/bit.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130511487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A programmable discrete-time filter employing hardware-efficient two-dimensional implementation method 一种采用硬件高效二维实现方法的可编程离散时间滤波器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008905
Jaeyoung Choi, M. Raja, M. A. Arasu
{"title":"A programmable discrete-time filter employing hardware-efficient two-dimensional implementation method","authors":"Jaeyoung Choi, M. Raja, M. A. Arasu","doi":"10.1109/ASSCC.2014.7008905","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008905","url":null,"abstract":"A programmable discrete-time (DT) filter for wideband wireless receivers is presented. A 2-dimensional DT FIR implementation method reduces the circuit complexity by creating a convolution between charge sharing and charge accumulation filters. The cascaded filter chain down-converts the input over a wide frequency band while limiting the variation in the output sample rate, which is accomplished by programming the decimation factor in proportion to the carrier frequency. The filter is fabricated in a 65 nm LP CMOS process for a proof-of-concept operation in the VHF band of 100-300 MHz. When the decimation factor is selected to be proportional to the input frequency, variations in gain and bandwidth were only 56.8-59.1 dB and 1.22-1.27 MHz. The filter rejects aliasing frequencies more than 35 dB over the wide input frequency range.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131715500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 5–20 Gb/s power scalable adaptive linear equalizer using edge counting 使用边缘计数的5 - 20gb /s功率可扩展自适应线性均衡器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008913
Yuanyuan Lin, Chang-Cheng Huang, J. Lee, Chih-Tien Chang, Shen-Iuan Liu
{"title":"A 5–20 Gb/s power scalable adaptive linear equalizer using edge counting","authors":"Yuanyuan Lin, Chang-Cheng Huang, J. Lee, Chih-Tien Chang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2014.7008913","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008913","url":null,"abstract":"A 5-20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The power of this CTLE is adjusted according to the bit rates to improve the power efficiency. An edge counting technique with an asynchronous clock is presented to adaptively adjust the gain and power of this CTLE. All the measured bit error rates are less than 10-12 over a 5m cable.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122896330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A reconfigurable analog baseband for single-chip, Saw-less, 2G/3G/4G cellular transceivers with carrier aggregation 一种可重构的模拟基带，用于带载波聚合的单片、无锯、2G/3G/4G蜂窝收发器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008847
Jongwoo Lee, Byungki Han, Jaewoo Lim, S. Ahn, Jaekwon Kim, T. Cho
{"title":"A reconfigurable analog baseband for single-chip, Saw-less, 2G/3G/4G cellular transceivers with carrier aggregation","authors":"Jongwoo Lee, Byungki Han, Jaewoo Lim, S. Ahn, Jaekwon Kim, T. Cho","doi":"10.1109/ASSCC.2014.7008847","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008847","url":null,"abstract":"This paper describes an analog baseband for single-chip 2G/3G/4G MIMO transceivers. By capacitor sharing technique and log tuning, the RX filter is programmable to set fc from 0.1 to 14MHz with 2% accuracy with 93dB gain range which is linear-in-dB. The TX filter suppresses DAC images and noise for Saw-less with constant or ramping envelope. A digital calibration adjusts fc, Q, and DC offset. The filter implemented in 65nm CMOS, occupies 2.79mm2, and consumes 7.3/8.4/10.2mW with 1.2V supply for 2G/3G/4G, respectively. This chip is in mass production for handheld products.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124465795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 0.1–1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration 一种带有混合8相LO发生器、相位模糊校正和矢量增益校准的0.1-1.5GHz谐波抑制接收机前端
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008933
Xinwang Zhang, Zhihua Wang, B. Chi
{"title":"A 0.1–1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration","authors":"Xinwang Zhang, Zhihua Wang, B. Chi","doi":"10.1109/ASSCC.2014.7008933","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008933","url":null,"abstract":"A 0.1-1.5GHz harmonic rejection (HR) receiver front-end is presented. A flexible HR mixer is proposed to correct phase ambiguity, and a vector gain calibration is used to eliminate the gain/phase mismatch and improve the HR ratio. With the proposed hybrid 8 phase local oscillating (LO) generator, the highest carrier frequency from the frequency synthesizer is only twice of the desired LO frequency. The HR receiver has been implemented in 65nm CMOS. With 1.8mm2 core chip area and 5.4-24.5mA current consumption from a 1.2V power supply, the receiver achieves 85dB conversion gain, 4.3dB NF, +13dBm/+14dBm IB/OB-IIP3, >54/56 dB HR3/HR5 with 30-40dB improvement by calibration, and 2.3% EVM with 32QAM modulation signal.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127689892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low-input-swing AC-DC voltage multiplier using Schottky diodes 一种使用肖特基二极管的低输入摆幅交直流电压倍增器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008906
Y. Luo, Shen-Iuan Liu
{"title":"A low-input-swing AC-DC voltage multiplier using Schottky diodes","authors":"Y. Luo, Shen-Iuan Liu","doi":"10.1109/ASSCC.2014.7008906","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008906","url":null,"abstract":"A low-input-swing AC-DC voltage multiplier using Schottky diodes is presented. The equivalent model of the voltage multiplier is developed and analyzed. To enhance power conversion efficiency (PCE), a matching network is added. For a multiple-stage voltage multiplier, a limiting circuit is added for over-voltage protection. A single-stage/three-stage voltage multiplier with a limiting circuit is fabricated in a 0.18μm CMOS technology and its area is equal to 0.761mm2. With the matching network, the measured maximum PCE are 31.4% and 35.8% when input amplitudes are 60mV and 160mV for a single-stage voltage multiplier and a three-stage one, respectively, at input frequency of 1MHz.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126069106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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