A 0.43pJ/bit true random number generator

Abstract

A small-area energy-efficient true random number generator (TRNG) is presented. This TRNG introduces a jitter signal generator to realize the noise pre-amplification, and utilizes a metastable latch to resolve the jitter edges. Moreover, to tolerate the process and environment variations, an offset calibration is employed to dynamically correct the bias of the probability of logic 0/1 in background. A prototype is fabricated in 40-nm CMOS technology. It occupies an area of 0.0014mm2 and consumes 214nW from a 0.8-V supply at a throughput of 500kbps. The proposed TRNG passes the NIST tests, and its calculated FOM is 0.43pJ/bit.