A programmable discrete-time filter employing hardware-efficient two-dimensional implementation method

Abstract

A programmable discrete-time (DT) filter for wideband wireless receivers is presented. A 2-dimensional DT FIR implementation method reduces the circuit complexity by creating a convolution between charge sharing and charge accumulation filters. The cascaded filter chain down-converts the input over a wide frequency band while limiting the variation in the output sample rate, which is accomplished by programming the decimation factor in proportion to the carrier frequency. The filter is fabricated in a 65 nm LP CMOS process for a proof-of-concept operation in the VHF band of 100-300 MHz. When the decimation factor is selected to be proportional to the input frequency, variations in gain and bandwidth were only 56.8-59.1 dB and 1.22-1.27 MHz. The filter rejects aliasing frequencies more than 35 dB over the wide input frequency range.