使用边缘计数的5 - 20gb /s功率可扩展自适应线性均衡器

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI:10.1109/ASSCC.2014.7008913

Yuanyuan Lin, Chang-Cheng Huang, J. Lee, Chih-Tien Chang, Shen-Iuan Liu

{"title":"使用边缘计数的5 - 20gb /s功率可扩展自适应线性均衡器","authors":"Yuanyuan Lin, Chang-Cheng Huang, J. Lee, Chih-Tien Chang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2014.7008913","DOIUrl":null,"url":null,"abstract":"A 5-20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The power of this CTLE is adjusted according to the bit rates to improve the power efficiency. An edge counting technique with an asynchronous clock is presented to adaptively adjust the gain and power of this CTLE. All the measured bit error rates are less than 10-12 over a 5m cable.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A 5–20 Gb/s power scalable adaptive linear equalizer using edge counting\",\"authors\":\"Yuanyuan Lin, Chang-Cheng Huang, J. Lee, Chih-Tien Chang, Shen-Iuan Liu\",\"doi\":\"10.1109/ASSCC.2014.7008913\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 5-20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The power of this CTLE is adjusted according to the bit rates to improve the power efficiency. An edge counting technique with an asynchronous clock is presented to adaptively adjust the gain and power of this CTLE. All the measured bit error rates are less than 10-12 over a 5m cable.\",\"PeriodicalId\":161031,\"journal\":{\"name\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"77 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2014.7008913\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2014.7008913","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 12

摘要

采用40纳米CMOS技术制作了一种5-20Gb/s功率可扩展的自适应连续时间线性均衡器(CTLE)。该CTLE可根据比特率调整功率，提高电源效率。提出了一种带异步时钟的边缘计数技术，可自适应调节CTLE的增益和功率。在5m电缆上测量的误码率均小于10 ~ 12。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 5–20 Gb/s power scalable adaptive linear equalizer using edge counting

A 5-20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The power of this CTLE is adjusted according to the bit rates to improve the power efficiency. An edge counting technique with an asynchronous clock is presented to adaptively adjust the gain and power of this CTLE. All the measured bit error rates are less than 10-12 over a 5m cable.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)

自引率

0.00%

发文量