Jongwoo Lee, Byungki Han, Jaewoo Lim, S. Ahn, Jaekwon Kim, T. Cho
{"title":"A reconfigurable analog baseband for single-chip, Saw-less, 2G/3G/4G cellular transceivers with carrier aggregation","authors":"Jongwoo Lee, Byungki Han, Jaewoo Lim, S. Ahn, Jaekwon Kim, T. Cho","doi":"10.1109/ASSCC.2014.7008847","DOIUrl":null,"url":null,"abstract":"This paper describes an analog baseband for single-chip 2G/3G/4G MIMO transceivers. By capacitor sharing technique and log tuning, the RX filter is programmable to set fc from 0.1 to 14MHz with 2% accuracy with 93dB gain range which is linear-in-dB. The TX filter suppresses DAC images and noise for Saw-less with constant or ramping envelope. A digital calibration adjusts fc, Q, and DC offset. The filter implemented in 65nm CMOS, occupies 2.79mm2, and consumes 7.3/8.4/10.2mW with 1.2V supply for 2G/3G/4G, respectively. This chip is in mass production for handheld products.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2014.7008847","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
This paper describes an analog baseband for single-chip 2G/3G/4G MIMO transceivers. By capacitor sharing technique and log tuning, the RX filter is programmable to set fc from 0.1 to 14MHz with 2% accuracy with 93dB gain range which is linear-in-dB. The TX filter suppresses DAC images and noise for Saw-less with constant or ramping envelope. A digital calibration adjusts fc, Q, and DC offset. The filter implemented in 65nm CMOS, occupies 2.79mm2, and consumes 7.3/8.4/10.2mW with 1.2V supply for 2G/3G/4G, respectively. This chip is in mass production for handheld products.