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2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier 一种采用动态放大器的0.5 ~ 1v 9位15 ~ 90ms /s数字插值的流水线sar ADC
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008866
James Lin, Zule Xu, M. Miyahara, A. Matsuzawa
{"title":"A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier","authors":"James Lin, Zule Xu, M. Miyahara, A. Matsuzawa","doi":"10.1109/ASSCC.2014.7008866","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008866","url":null,"abstract":"This paper presents a 0.5-to-1 V, 9-bit, 15-to-90 MS/s digitally interpolated pipelined-SAR ADC. The proposed digital interpolation alleviates the inter-stage gain requirement of a pipelined-SAR ADC making this ADC insensitive to gain variation. With a relaxed gain requirement, an open-loop dynamic amplifier is employed as the residue amplifier making the proposed design high-speed, clock-scalable, and robust to supply voltage scaling. The prototype ADC fabricated in 65 nm CMOS demonstrates an ENOB of 7.88 bits up to 30 MS/s with an input close to the Nyquist frequency at 0.6 V. At this conversion rate, it consumes 0.48 mW resulting in a FoM of 68 fJ/conv.-step.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127495901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Internet of Things: Evolution towards a hyper-connected society 物联网:向超连接社会的进化
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008846
A. Choi
{"title":"Internet of Things: Evolution towards a hyper-connected society","authors":"A. Choi","doi":"10.1109/ASSCC.2014.7008846","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008846","url":null,"abstract":"Internet of Things is expected to encompass every aspect of our lives and to generate a paradigm shift towards a hyper-connected society. As more things are connected to the Internet, larger amount of data are generated and processed into useful actions that can make our lives safer and easier. Since IoT generate heavy traffics, it induces several challenges to next generation network. Therefore, IoT infrastructure should be designed in terms of flexibility and scalability. In addition, cloud computing and big data analytics are being integrated. They allow network to change itself much faster to service requirements with better operational efficiency and intelligence. IoT should also be vertically optimized from device to application in order to provide ultra-low power operation, cost-effectiveness, and service reliability with ensuring full security across the entire signal path. In this paper we address IoT challenges and technological requirements from the service provider perspective.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121591252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS 一个3mhz -1.8 GHz 94 μ w -9.5 mW 0.0153-mm2的65nm CMOS全数字延时锁相环
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008935
Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, C. Sun, Yuan-Hua Chu, Tzu-Yi Yang
{"title":"A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS","authors":"Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, C. Sun, Yuan-Hua Chu, Tzu-Yi Yang","doi":"10.1109/ASSCC.2014.7008935","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008935","url":null,"abstract":"It is challenging to design a closed-loop all-digital delay-locked loop (ADDLL) that also has a small area, low power, and fast locking for a wide frequency range operation. In this work a cyclic half-delay-line architecture with the same type of delay lines for cyclic delay deduction and coarse locking is proposed to achieve the design goals of small area and fast locking for a wide frequency range operation. In addition to clock gating, which is used to reduce power consumption in the lock-in state regardless of the clock frequency, automatic bypassing of the cyclic operation is developed to reduce power consumption for high-frequency operations. Based on these proposed techniques, a 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 closed-loop ADDLL is realized in 65-nm CMOS.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"153 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134034433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A power management unit integrated ADSL/ADSL2+ CPE analog front-end with −93.5dB THD for DMT-based applications 电源管理单元集成了ADSL/ADSL2+ CPE模拟前端，THD为−93.5dB，适用于基于dmt的应用
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008873
Yu-Kai Chou, Yue Feng, Yu-Hsin Lin, Cong Liu, Chen-Yen Ho, B. Hu, Jun Zha, S. Chuang
{"title":"A power management unit integrated ADSL/ADSL2+ CPE analog front-end with −93.5dB THD for DMT-based applications","authors":"Yu-Kai Chou, Yue Feng, Yu-Hsin Lin, Cong Liu, Chen-Yen Ho, B. Hu, Jun Zha, S. Chuang","doi":"10.1109/ASSCC.2014.7008873","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008873","url":null,"abstract":"This paper presents a high linear analog front-end (AFE) for ADSL/ADSL2+ system applications. This AFE has the overall linearity of -93.5dB to ensure the ADSL/ADSL2+ modem to achieve up to 27.2Mbps down-stream data-rate on short loops. The AFE is implemented in two chips using 0.11um/55nm CMOS process with integrated power management unit (PMU) to optimize the data-rate, die area and power efficiency. The choice of the process is a compromise between the size of the digital circuits, and the analog performance and cost. Furthermore, a 90dB dynamic range (DR) CTSDM ADC is employed to relax the requirement of the front-end filters of the receiver, and thus the filter orders are reduced as well as the area and power consumption. The transmit path can achieve 90dB SNR and -95.2dB THD. The receive path can achieve 82.1dB SNR and -93.5dB THD. The AFE including line driver using the dual-chip solution dissipates 590 mW from 3.3V/5 V supply.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114475734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor 一个0.4V 280 nw无频率参考几乎全数字混合域温度传感器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008920
Wenfeng Zhao, Rui Pan, Yajun Ha, Zhi Yang
{"title":"A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor","authors":"Wenfeng Zhao, Rui Pan, Yajun Ha, Zhi Yang","doi":"10.1109/ASSCC.2014.7008920","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008920","url":null,"abstract":"This paper presents a subthreshold frequency reference-less temperature sensor. Compared with the previous designs that rely on external frequency references or excessive analog blocks, this work proposes a novel subthreshold ratioed-current/delay sensor core and hybrid-domain all-digital processing technique, which eliminates the dependence on frequency reference and is scalable to technology feature size. Our sensor has been fabricated in a 65-nm CMOS process and occupies a total area of 0.022mm2. Measurement results from 8 test chips have shown that the maximum inaccuracy is -1.6oC/+1oC across 0oC to 100oC with power consumption of 280-nW at 0.4V.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133754387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration 一个12位250 MS/s 28 mW +70 dB SFDR DAC，采用0.11 μm CMOS，采用可控RZ窗口，用于无线SoC集成
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008868
Seonggeon Kim, Jaehyun Kang, Minjae Lee
{"title":"A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration","authors":"Seonggeon Kim, Jaehyun Kang, Minjae Lee","doi":"10.1109/ASSCC.2014.7008868","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008868","url":null,"abstract":"A 12 bit CMOS current-steering digital-to-analog converter (DAC) in 0.11 μm CMOS technology is presented for IQ baseband wireless transmitter and envelop tracking (ET) power amplifier that requires low power consumption with flexible swing and common-mode controls. The conventional half clock period return-to-zero (RZ) effectively eliminates code-dependent transient but results in amplitude loss. The proposed controllable RZ window less than 50 % of clock duty cycle mitigates such signal loss, and yet achieves the spurious-free dynamic range (SFDR) better than 70 dB up to Nyquist bandwidth at the sample frequency of 250 MHz. The core area of DAC is 0.117 mm2 and it dissipates about 28 mW under 2.5 V supply.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133239945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CCM/GM relative skip energy control in single-inductor multiple-output DC-DC converter for wearable device power solution 可穿戴设备电源解决方案中单电感多输出DC-DC变换器的CCM/GM相对跳过能量控制
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008861
Yi-Ping Su, Chiun-He Lin, Te-Fu Yang, Ru-Yu Huang, Wei-Chung Chen, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chao-Cheng Lee
{"title":"CCM/GM relative skip energy control in single-inductor multiple-output DC-DC converter for wearable device power solution","authors":"Yi-Ping Su, Chiun-He Lin, Te-Fu Yang, Ru-Yu Huang, Wei-Chung Chen, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chao-Cheng Lee","doi":"10.1109/ASSCC.2014.7008861","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008861","url":null,"abstract":"Compact size wearable devices require multiple supplies with relative large loading difference, which causes serious cross regulation, large ripple and oscillation in single-inductor multiple-output (SIMO) DC-DC converter. Thus, a continuous conduction mode/green mode (CCM/GM) relative skip energy control (RSEC) in single-inductor multiple-output (SIMO) is proposed for wearable device power solution. Different from conventional absolute skip method, the RSEC eliminates unnecessary skip-induced voltage ripple and cross regulation with well regulation performance over wide load and voltage ranges. Optimization between efficiency and voltage ripple achieves low noise supply and reduced switching loss. Moreover, smooth transition between CCM and GM provides high power and longer usage time in wearable devices. The test chip fabricated in 0.18μm CMOS process occupies 2.24mm2 active area. Maximum output ripple, overshoot/undershoot and cross regulation are kept below 17mV, 27mV and 0.0432mV/mA, respectively.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133546227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI 在28nm FD SOI中，具有0.011 mm2 ppt鲁棒性的完全合成CDR，数据速率为10.05 Gb/s
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008916
A. Narayanan, W. Deng, Dongsheng Yang, Rui Wu, K. Okada, A. Matsuzawa
{"title":"A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI","authors":"A. Narayanan, W. Deng, Dongsheng Yang, Rui Wu, K. Okada, A. Matsuzawa","doi":"10.1109/ASSCC.2014.7008916","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008916","url":null,"abstract":"This paper presents a fully-synthesizable clock and data recovery circuit using injection locking technique. The challenges presented by automated place and route for high speed applications is overcome using background calibration mechanism. The fully-synthesizable all-digital architecture presented in this work is fabricated in 28nm FDSOI technology. The system has a top data-rate of 10.05Gb/s while consuming 16mW power from 1.0V supply.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124069172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 12-V charge pump-based square wave driver in 65-nm CMOS technology 基于65nm CMOS技术的12v电荷泵方波驱动器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008904
Yousr Ismail, C. Yang
{"title":"A 12-V charge pump-based square wave driver in 65-nm CMOS technology","authors":"Yousr Ismail, C. Yang","doi":"10.1109/ASSCC.2014.7008904","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008904","url":null,"abstract":"This paper presents a high-voltage output stage producing signals well beyond the voltage ratings of standard devices in a nanometer-scale CMOS technology. The driver is a two-level, switched capacitor output stage that combines both voltage conversion and pulse drive. The design is highly modular and enables extended device-stacking seamlessly and with little overhead. The driver achieves a peak power efficiency of 64%, a minimum drive resistance of 3.7KΩ and occupies an area of 0.06mm2.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130260555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
CMOS THz transmissive imaging system CMOS太赫兹透射成像系统
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008887
Tzu-Chao Yan, Chun-Hsing Li, Chih-Wei Lai, Wei-Cheng Chen, T. Chao, C. Kuo
{"title":"CMOS THz transmissive imaging system","authors":"Tzu-Chao Yan, Chun-Hsing Li, Chih-Wei Lai, Wei-Cheng Chen, T. Chao, C. Kuo","doi":"10.1109/ASSCC.2014.7008887","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008887","url":null,"abstract":"This paper presents a THz imaging system composed of a signal source and a signal sensor in CMOS technology. The signal source integrates a 338 GHz oscillator in 40-nm CMOS and an antenna array on a Benzocyclobutene (BCB) carrier using the SoP (System-on-Package) technique. The measured EIRP achieves +8 dBm. The signal sensor is implemented in 0.18 μm CMOS. The measured maximum responsivity is 632 kV/W at 332 GHz. The signal source and signal sensor consume dc power of 37.5 mW and 7.92 mW, respectively. The resolution of the proposed THz imaging system is 4 mm.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117100558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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