A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI

Abstract

This paper presents a fully-synthesizable clock and data recovery circuit using injection locking technique. The challenges presented by automated place and route for high speed applications is overcome using background calibration mechanism. The fully-synthesizable all-digital architecture presented in this work is fabricated in 28nm FDSOI technology. The system has a top data-rate of 10.05Gb/s while consuming 16mW power from 1.0V supply.