电源管理单元集成了ADSL/ADSL2+ CPE模拟前端,THD为−93.5dB,适用于基于dmt的应用

Yu-Kai Chou, Yue Feng, Yu-Hsin Lin, Cong Liu, Chen-Yen Ho, B. Hu, Jun Zha, S. Chuang
{"title":"电源管理单元集成了ADSL/ADSL2+ CPE模拟前端,THD为−93.5dB,适用于基于dmt的应用","authors":"Yu-Kai Chou, Yue Feng, Yu-Hsin Lin, Cong Liu, Chen-Yen Ho, B. Hu, Jun Zha, S. Chuang","doi":"10.1109/ASSCC.2014.7008873","DOIUrl":null,"url":null,"abstract":"This paper presents a high linear analog front-end (AFE) for ADSL/ADSL2+ system applications. This AFE has the overall linearity of -93.5dB to ensure the ADSL/ADSL2+ modem to achieve up to 27.2Mbps down-stream data-rate on short loops. The AFE is implemented in two chips using 0.11um/55nm CMOS process with integrated power management unit (PMU) to optimize the data-rate, die area and power efficiency. The choice of the process is a compromise between the size of the digital circuits, and the analog performance and cost. Furthermore, a 90dB dynamic range (DR) CTSDM ADC is employed to relax the requirement of the front-end filters of the receiver, and thus the filter orders are reduced as well as the area and power consumption. The transmit path can achieve 90dB SNR and -95.2dB THD. The receive path can achieve 82.1dB SNR and -93.5dB THD. The AFE including line driver using the dual-chip solution dissipates 590 mW from 3.3V/5 V supply.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A power management unit integrated ADSL/ADSL2+ CPE analog front-end with −93.5dB THD for DMT-based applications\",\"authors\":\"Yu-Kai Chou, Yue Feng, Yu-Hsin Lin, Cong Liu, Chen-Yen Ho, B. Hu, Jun Zha, S. Chuang\",\"doi\":\"10.1109/ASSCC.2014.7008873\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a high linear analog front-end (AFE) for ADSL/ADSL2+ system applications. This AFE has the overall linearity of -93.5dB to ensure the ADSL/ADSL2+ modem to achieve up to 27.2Mbps down-stream data-rate on short loops. The AFE is implemented in two chips using 0.11um/55nm CMOS process with integrated power management unit (PMU) to optimize the data-rate, die area and power efficiency. The choice of the process is a compromise between the size of the digital circuits, and the analog performance and cost. Furthermore, a 90dB dynamic range (DR) CTSDM ADC is employed to relax the requirement of the front-end filters of the receiver, and thus the filter orders are reduced as well as the area and power consumption. The transmit path can achieve 90dB SNR and -95.2dB THD. The receive path can achieve 82.1dB SNR and -93.5dB THD. The AFE including line driver using the dual-chip solution dissipates 590 mW from 3.3V/5 V supply.\",\"PeriodicalId\":161031,\"journal\":{\"name\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"150 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2014.7008873\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2014.7008873","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

本文介绍了一种用于ADSL/ADSL2+系统的高线性模拟前端(AFE)。该AFE的整体线性度为-93.5dB,可确保ADSL/ADSL2+调制解调器在短环路下实现高达27.2Mbps的下行数据速率。该AFE采用0.11um/55nm CMOS工艺和集成电源管理单元(PMU)在两个芯片中实现,以优化数据速率,芯片面积和功率效率。该工艺的选择是在数字电路的尺寸,模拟性能和成本之间的折衷。此外,采用90dB动态范围(DR) CTSDM ADC,降低了对接收机前端滤波器的要求,从而减少了滤波器的阶数,降低了面积和功耗。发射路径信噪比可达90dB, THD可达-95.2dB。接收路径信噪比可达82.1dB, THD可达-93.5dB。使用双芯片解决方案的AFE包括线路驱动器,从3.3V/5 V电源消耗590mw。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A power management unit integrated ADSL/ADSL2+ CPE analog front-end with −93.5dB THD for DMT-based applications
This paper presents a high linear analog front-end (AFE) for ADSL/ADSL2+ system applications. This AFE has the overall linearity of -93.5dB to ensure the ADSL/ADSL2+ modem to achieve up to 27.2Mbps down-stream data-rate on short loops. The AFE is implemented in two chips using 0.11um/55nm CMOS process with integrated power management unit (PMU) to optimize the data-rate, die area and power efficiency. The choice of the process is a compromise between the size of the digital circuits, and the analog performance and cost. Furthermore, a 90dB dynamic range (DR) CTSDM ADC is employed to relax the requirement of the front-end filters of the receiver, and thus the filter orders are reduced as well as the area and power consumption. The transmit path can achieve 90dB SNR and -95.2dB THD. The receive path can achieve 82.1dB SNR and -93.5dB THD. The AFE including line driver using the dual-chip solution dissipates 590 mW from 3.3V/5 V supply.
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