Yu-Kai Chou, Yue Feng, Yu-Hsin Lin, Cong Liu, Chen-Yen Ho, B. Hu, Jun Zha, S. Chuang
{"title":"A power management unit integrated ADSL/ADSL2+ CPE analog front-end with −93.5dB THD for DMT-based applications","authors":"Yu-Kai Chou, Yue Feng, Yu-Hsin Lin, Cong Liu, Chen-Yen Ho, B. Hu, Jun Zha, S. Chuang","doi":"10.1109/ASSCC.2014.7008873","DOIUrl":null,"url":null,"abstract":"This paper presents a high linear analog front-end (AFE) for ADSL/ADSL2+ system applications. This AFE has the overall linearity of -93.5dB to ensure the ADSL/ADSL2+ modem to achieve up to 27.2Mbps down-stream data-rate on short loops. The AFE is implemented in two chips using 0.11um/55nm CMOS process with integrated power management unit (PMU) to optimize the data-rate, die area and power efficiency. The choice of the process is a compromise between the size of the digital circuits, and the analog performance and cost. Furthermore, a 90dB dynamic range (DR) CTSDM ADC is employed to relax the requirement of the front-end filters of the receiver, and thus the filter orders are reduced as well as the area and power consumption. The transmit path can achieve 90dB SNR and -95.2dB THD. The receive path can achieve 82.1dB SNR and -93.5dB THD. The AFE including line driver using the dual-chip solution dissipates 590 mW from 3.3V/5 V supply.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2014.7008873","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a high linear analog front-end (AFE) for ADSL/ADSL2+ system applications. This AFE has the overall linearity of -93.5dB to ensure the ADSL/ADSL2+ modem to achieve up to 27.2Mbps down-stream data-rate on short loops. The AFE is implemented in two chips using 0.11um/55nm CMOS process with integrated power management unit (PMU) to optimize the data-rate, die area and power efficiency. The choice of the process is a compromise between the size of the digital circuits, and the analog performance and cost. Furthermore, a 90dB dynamic range (DR) CTSDM ADC is employed to relax the requirement of the front-end filters of the receiver, and thus the filter orders are reduced as well as the area and power consumption. The transmit path can achieve 90dB SNR and -95.2dB THD. The receive path can achieve 82.1dB SNR and -93.5dB THD. The AFE including line driver using the dual-chip solution dissipates 590 mW from 3.3V/5 V supply.