A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier

Abstract

This paper presents a 0.5-to-1 V, 9-bit, 15-to-90 MS/s digitally interpolated pipelined-SAR ADC. The proposed digital interpolation alleviates the inter-stage gain requirement of a pipelined-SAR ADC making this ADC insensitive to gain variation. With a relaxed gain requirement, an open-loop dynamic amplifier is employed as the residue amplifier making the proposed design high-speed, clock-scalable, and robust to supply voltage scaling. The prototype ADC fabricated in 65 nm CMOS demonstrates an ENOB of 7.88 bits up to 30 MS/s with an input close to the Nyquist frequency at 0.6 V. At this conversion rate, it consumes 0.48 mW resulting in a FoM of 68 fJ/conv.-step.