2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献_第5页

54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique 54 GHz CMOS LNAs, NF 3.6 dB，增益28.2 dB，采用变压器反馈gm升压技术

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008891

Shita Guo, Tianzuo Xi, P. Gui, Jing Zhang, W. Choi, K. O. Kenneth, Yanli Fan, Daquan Huang, R. Gu, Mark Morgan

引用次数: 13

A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory 一种用于多级相变存储器的6位抗漂移读出方案

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008879

A. Athmanathan, M. Stanisavljevic, Junho Cheon, Seokjoon Kang, Changyong Ahn, Junghyuk Yoon, Min-Chul Shin, Taekseung Kim, N. Papandreou, H. Pozidis, E. Eleftheriou

{"title":"A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory","authors":"A. Athmanathan, M. Stanisavljevic, Junho Cheon, Seokjoon Kang, Changyong Ahn, Junghyuk Yoon, Min-Chul Shin, Taekseung Kim, N. Papandreou, H. Pozidis, E. Eleftheriou","doi":"10.1109/ASSCC.2014.7008879","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008879","url":null,"abstract":"Multiple-Level Cell (MLC) storage provides increased capacity and hence reduced cost-per-bit in memory technologies, thereby rendering such technologies suitable for big data applications. In Phase-Change Memory (PCM), however, MLC storage is seriously hampered by the phenomenon of resistance drift. We present a readout circuit for PCM specifically designed for drift resilience in MLC operation. Drift resilience is achieved through the use of specific non-resistance-based cell-state metrics which, in contrast to the traditional cell-state metric, i.e., the low-field electrical resistance, have built-in drift robustness. The circuit provides a fast and efficient implementation of drift-resilient metric, enabling, for the first time, the performance required by non volatile memory applications. In addition, by exploiting the non linear sub-threshold I-V characteristics of PCM cells, the readout architecture promises to increase the distinguishable signal range. The proposed read circuitry is designed and fabricated in 64-nm CMOS technology. Experimental results using an integrated test resistor array for readout circuit characterization are presented, demonstrating access time of 450 ns at 6-bit raw (5-bit effective) resolution. The circuit has low-noise characteristics and does not exhibit sensitivity to bit-line parasitics. The readout circuit is co-integrated with a 16 Mb 2x-nm PCM cell array and the necessary programming electronics.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124281593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Semiconductor innovation into the next decade 半导体创新进入下一个十年

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008874

Jack Sun

引用次数: 2

A 23mW/lane 1.2–6.8Gb/s multi-standard transceiver in 28nm CMOS 采用28nm CMOS的23mW/lane 1.2-6.8Gb /s多标准收发器

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008871

Seong-Ho Lee, D. Tran, Tamer A. Ali, B. Çatli, Heng Zhang, Wei Zhang, Mohammed M. Abdul-Latif, Z. Huang, Guansheng Li, Mahmoud Reza Ahmadi, A. Momtaz

引用次数: 1

A 1.44mm2 4-channel UWB beamforming receiver with Q-compensation in 65nm CMOS 基于65nm CMOS的1.44mm2 4通道超宽带q补偿波束成形接收机

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008908

Lei Wang, Y. Lian, C. Heng

引用次数: 5

A sub-threshold to super-threshold Level Conversion Flip Flop for sub/near-threshold dual-supply operation 亚阈值到超阈值电平转换触发器，用于亚/近阈值双电源操作

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008855

引用次数: 1

A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS 一个完全集成的可重构双频收发器，用于180nm CMOS的短距离无线通信

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008909

Xiaobao Yu, Meng Wei, Yun Yin, Ying Song, Siyang Han, Qiongbing Liu, Zongming Jin, Xiliang Liu, Zhihua Wang, B. Chi

{"title":"A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS","authors":"Xiaobao Yu, Meng Wei, Yun Yin, Ying Song, Siyang Han, Qiongbing Liu, Zongming Jin, Xiliang Liu, Zhihua Wang, B. Chi","doi":"10.1109/ASSCC.2014.7008909","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008909","url":null,"abstract":"A fully-integrated reconfigurable dual-band transceiver (TRX) is presented for short range wireless communication. The TRX has two independent RF front-ends for each band with a shared analog baseband to achieve optimum power and cost. In Sub-GHz (760-960MHz) band, the maximum 75dBc 3rd harmonic rejection ratio (HRR) is achieved by inserting a RFA with notch filtering. In 2.4GHz band, a single-ended-to-differential (S2D) RFA with phase and gain error compensation is proposed. By optimizing two bands separately, the RX achieves a NF of 5.1dB and 4.2dB, respectively. A Σ-Δ fractional-N PLL with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the multi-mode CMOS PAs are integrated, which achieve the measured output P1dB (OP1dB) of 16.3dBm and 14.8dBm with 25% PAE for Sub-GHz and 2.4GHz bands. Furthermore, to optimize the PA's back-off efficiency, the power-control loop is proposed to detect the input signal PAPR in real time and flexibly reconfigure the PA's operation modes. With this proposed technique, the PAE in Sub-GHz band is improved by ×3.24 and ×1.41 at 9dB and 3dB back-off powers. In 2.4GHz band, the PAE is improved by ×2.17 at 6dB back-off power. The measured results have demonstrated that this presented transceiver has achieved comparable or even better performance in terms of noise, HRR, OP1dB and power efficiency compared with the-state-of-the-arts.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125797742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology 完全集成的40 gb /s脉冲模式发生器和误码率测试仪芯片组，采用65纳米CMOS技术

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008872

Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

引用次数: 1

A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback 具有数字ELD补偿和多位FIR反馈的1 V 59 fJ/Step 15 MHz BW 74 dB SNDR连续时间ΔΣ调制器

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008925

Yi Zhang, Chia-Hung Chen, Tao He, Xin Meng, N. Qian, E. Liu, Phillip Elliott, G. Temes

引用次数: 4

A 20MS/s buck/boost supply modulator for envelope tracking applications with direct digital interface 20MS/s降压/升压电源调制器，用于包络跟踪应用，具有直接数字接口

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008863

Shang-Hsien Yang, Chinder Wey, Ke-Horng Chen, Ying-Hsi Lin, Jing-Jia Chen, Tsung-Yen Tsai, Chao-Cheng Lee

引用次数: 1