完全集成的40 gb /s脉冲模式发生器和误码率测试仪芯片组，采用65纳米CMOS技术

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI:10.1109/ASSCC.2014.7008872

Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

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引用次数: 1

摘要

采用65纳米CMOS技术的40 gb /s脉冲模式发生器(PPG)和误码率测试仪(BERT)芯片组已被完全集成。使用外部时钟输入，PPG和BERT可以在40 Mb/s到40 Gb/s的超宽数据范围内实现全面运行。还包括内置锁相环和CDR电路，为标准规格测试提供健壮性。

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Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology

Fully-integrated 40-Gb/s pulse pattern generator (PPG) and bit-error-rate tester (BERT) chipsets has been presented in 65-nm CMOS technology. Using external clock inputs, the PPG and BERT achieve full operation with ultra-wide data range from 40 Mb/s to 40 Gb/s. Built-in PLL and CDR circuits are also included to provide robustness for standard specification testing.

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2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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