A 23mW/lane 1.2–6.8Gb/s multi-standard transceiver in 28nm CMOS

Abstract

This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology. Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2-6.8Gb/s while supporting a wide range of communication standards, including SGMII, QSGMII, PCIE, SATA, USB3, XAUI and RXAUI. Power consumption per lane is 23mW at 0.9V for SATA3 at 6Gb/s, with an area of 0.265mm2 for a single-lane transceiver with PLL.