A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory

Multiple-Level Cell (MLC) storage provides increased capacity and hence reduced cost-per-bit in memory technologies, thereby rendering such technologies suitable for big data applications. In Phase-Change Memory (PCM), however, MLC storage is seriously hampered by the phenomenon of resistance drift. We present a readout circuit for PCM specifically designed for drift resilience in MLC operation. Drift resilience is achieved through the use of specific non-resistance-based cell-state metrics which, in contrast to the traditional cell-state metric, i.e., the low-field electrical resistance, have built-in drift robustness. The circuit provides a fast and efficient implementation of drift-resilient metric, enabling, for the first time, the performance required by non volatile memory applications. In addition, by exploiting the non linear sub-threshold I-V characteristics of PCM cells, the readout architecture promises to increase the distinguishable signal range. The proposed read circuitry is designed and fabricated in 64-nm CMOS technology. Experimental results using an integrated test resistor array for readout circuit characterization are presented, demonstrating access time of 450 ns at 6-bit raw (5-bit effective) resolution. The circuit has low-noise characteristics and does not exhibit sensitivity to bit-line parasitics. The readout circuit is co-integrated with a 16 Mb 2x-nm PCM cell array and the necessary programming electronics.