在28nm FD SOI中，具有0.011 mm2 ppt鲁棒性的完全合成CDR，数据速率为10.05 Gb/s

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI:10.1109/ASSCC.2014.7008916

A. Narayanan, W. Deng, Dongsheng Yang, Rui Wu, K. Okada, A. Matsuzawa

{"title":"在28nm FD SOI中，具有0.011 mm2 ppt鲁棒性的完全合成CDR，数据速率为10.05 Gb/s","authors":"A. Narayanan, W. Deng, Dongsheng Yang, Rui Wu, K. Okada, A. Matsuzawa","doi":"10.1109/ASSCC.2014.7008916","DOIUrl":null,"url":null,"abstract":"This paper presents a fully-synthesizable clock and data recovery circuit using injection locking technique. The challenges presented by automated place and route for high speed applications is overcome using background calibration mechanism. The fully-synthesizable all-digital architecture presented in this work is fabricated in 28nm FDSOI technology. The system has a top data-rate of 10.05Gb/s while consuming 16mW power from 1.0V supply.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI\",\"authors\":\"A. Narayanan, W. Deng, Dongsheng Yang, Rui Wu, K. Okada, A. Matsuzawa\",\"doi\":\"10.1109/ASSCC.2014.7008916\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a fully-synthesizable clock and data recovery circuit using injection locking technique. The challenges presented by automated place and route for high speed applications is overcome using background calibration mechanism. The fully-synthesizable all-digital architecture presented in this work is fabricated in 28nm FDSOI technology. The system has a top data-rate of 10.05Gb/s while consuming 16mW power from 1.0V supply.\",\"PeriodicalId\":161031,\"journal\":{\"name\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2014.7008916\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2014.7008916","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文提出了一种采用注入锁定技术的完全可合成时钟和数据恢复电路。利用后台校准机制克服了高速应用中自动放置和路径所带来的挑战。这项工作中提出的完全可合成的全数字架构采用28nm FDSOI技术制造。该系统的最高数据速率为10.05Gb/s，在1.0V电源下消耗16mW功率。

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A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI

This paper presents a fully-synthesizable clock and data recovery circuit using injection locking technique. The challenges presented by automated place and route for high speed applications is overcome using background calibration mechanism. The fully-synthesizable all-digital architecture presented in this work is fabricated in 28nm FDSOI technology. The system has a top data-rate of 10.05Gb/s while consuming 16mW power from 1.0V supply.

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2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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