A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator

Abstract

Conventional processors are energy in-efficient in that they fail to utilize the fact that most of their time and energy are spent on heavily-recursively executed small code segments. A DYNaSTA accelerator, proposed and implemented, is an architectural solution to such a problem. It is an reconfigurable array accelerator featuring an hybrid architecture: only a limited portion is reconfigured dynamically (i.e., frequently) while the rest is reconfigured statically (i.e., only occasionally). This way, the DYNaSTA accelerator tries to achieve both flexibility and energy-efficiency at the same time. Results of power simulation and fabricated chip measurements have been quite encouraging: 4.5 to 13 times energy efficiency will be made possible by this accelerator when compared with a conventional embedded microprocessor.