A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process

Abstract

This paper presents a 26.5 Gb/s optical receiver with an all-digital CDR (ADCDR) fabricated in a 65 nm CMOS process. The receiver consists of a transimpedance amplifier (TIA), a limiting amplifier (LA), and a half-rate ADCDR. The TIA and LA are based on an inverter-based amplifier for low power consumption. The ADCDR adopts an LC quadrature digitally controlled oscillator (LC-QDCO) for the quadrature sampling. The recovered clock jitter is 1.28 psrms and the measured jitter tolerance exceeds the tolerance mask specified in IEEE 802.3ba. The receiver sensitivity is measured to be -9 dBm and -6.6 dBm for the data rate of 25 Gb/s and 26.5 Gb/s, respectively. The whole receiver chip occupies an active area of 0.75 mm2 and consumes 254 mW at the data rate of 26.5 Gb/s.