Yifan YangGong, Sebastian Turullols, Daniel Woo, Chang-Yang Huang, King C. Yen, V. Krishnaswamy, K. Holdbrook, Jinuk Luke Shin
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Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor
In order to minimize the impact of on-chip Ldi/dt noise on power and performance, Oracle's SPARC M6 processor features an Asymmetric Frequency Locked Loop (AFLL) that dynamically adjusts chip frequency. It achieves 15% improved noise immunity by reacting to the voltage noise asymmetrically through the use of a pair of DCO's that accurately track the response of critical paths. The AFLL is implemented in 28nm CMOS process in 0.045mm2 of area, dissipating 14mW, and reducing jitter by 50%.
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