40nm LP CMOS中0.3339 fj /bit/search高能效TCAM宏设计

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI:10.1109/ASSCC.2014.7008877

Po-Tsang Huang, Shu-Lin Lai, C. Chuang, W. Hwang, Jason Huang, A. Hu, Paul-Sen Kan, Michael Jia, Kimi Lv, B. Zhang

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引用次数: 5

摘要

本文设计并实现了一个256×40节能三元内容可寻址存储器(TCAM)宏，该宏采用40nm低功耗(LP) CMOS。针对LP工艺中栅极氧化物较厚的问题，提出了一种带有p型比较电路的16T TCAM电池，以提高动态电路的Ion/Ioff差。为了进一步提高能源效率，使用基于不关心的纹波搜索线/位线来减少开关活动和导线电容。此外，采用基于列的数据感知功率控制来降低泄漏功率和提高可写性。实验结果表明，TCAM宏的泄漏功率降低了28.9%，搜索线功率降低了31.74%，能量效率指标为0.339 fJ/bit/search。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS

In this paper, a 256×40 energy-efficient ternary content addressable memory (TCAM) macro is designed and implemented in 40nm low power (LP) CMOS. Due to the thicker gate oxide in LP process, a 16T TCAM cell with p-type comparison circuits is proposed to increase the Ion/Ioff difference of the dynamic circuitry. To further improve energy efficiency, don't-care-based ripple search-lines/bit-lines are used to reduce both the switching activities and wire capacitance. Moreover, column-based data-aware power control is employed for leakage power reduction and write-ability improvements. The experimental results show a leakage power reduction of 28.9%, a search-line power reduction of 31.74% and an energy efficiency metric of the TCAM macro of 0.339 fJ/bit/search.

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2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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