0.2 V 8T SRAM with improved bitline sensing using column-based data randomization

Abstract

8T SRAMs operating at sub-threshold supply voltages suffer from bit-line swing degradation when the data pattern of a column is dominated by `1' or `0'. Worst case scenarios happen when the accessed bit is different from the rest of the column. In this work, a simplified Linear Feedback Shift Register (LFSR) is used to shuffle input data so that distribution of “1” and “0” in each column is close to 50%. As a result, bit-line sensing margin is enhanced. In addition, a bitline boost biasing scheme is applied to further increase the bitline swing and the sensing window. A 16Kb test chips fabricated in a 65 nm CMOS technology demonstrates successful SRAM operation at 0.2 V, room temperate, having power consumption and access time of 0.7 μW and 2.5 μs, respectively.