A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS

Abstract

This paper presents a low-cost SAR ADC design for IEEE 802.11ac applications. A binary-scaled recombination weighting method for SAR ADC is disclosed in this work. The proposed SAR ADC achieved 9.29 ENOB with an FOM of 6.8 fJ/conversion-step at 0.9 V and 160 MS/s, and achieved 9.20 ENOB with an FOM of 8.1 fJ/conversion-step at 1.0 V and 320 MS/s. The ADC core only occupies an area of 33 μm × 35 μm in 20-nm CMOS process.