{"title":"10位320ms /s低成本SAR ADC，适用于20nm CMOS的IEEE 802.11ac应用","authors":"Chun-Cheng Liu","doi":"10.1109/ASSCC.2014.7008864","DOIUrl":null,"url":null,"abstract":"This paper presents a low-cost SAR ADC design for IEEE 802.11ac applications. A binary-scaled recombination weighting method for SAR ADC is disclosed in this work. The proposed SAR ADC achieved 9.29 ENOB with an FOM of 6.8 fJ/conversion-step at 0.9 V and 160 MS/s, and achieved 9.20 ENOB with an FOM of 8.1 fJ/conversion-step at 1.0 V and 320 MS/s. The ADC core only occupies an area of 33 μm × 35 μm in 20-nm CMOS process.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"73","resultStr":"{\"title\":\"A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS\",\"authors\":\"Chun-Cheng Liu\",\"doi\":\"10.1109/ASSCC.2014.7008864\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low-cost SAR ADC design for IEEE 802.11ac applications. A binary-scaled recombination weighting method for SAR ADC is disclosed in this work. The proposed SAR ADC achieved 9.29 ENOB with an FOM of 6.8 fJ/conversion-step at 0.9 V and 160 MS/s, and achieved 9.20 ENOB with an FOM of 8.1 fJ/conversion-step at 1.0 V and 320 MS/s. The ADC core only occupies an area of 33 μm × 35 μm in 20-nm CMOS process.\",\"PeriodicalId\":161031,\"journal\":{\"name\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"73\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2014.7008864\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2014.7008864","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS
This paper presents a low-cost SAR ADC design for IEEE 802.11ac applications. A binary-scaled recombination weighting method for SAR ADC is disclosed in this work. The proposed SAR ADC achieved 9.29 ENOB with an FOM of 6.8 fJ/conversion-step at 0.9 V and 160 MS/s, and achieved 9.20 ENOB with an FOM of 8.1 fJ/conversion-step at 1.0 V and 320 MS/s. The ADC core only occupies an area of 33 μm × 35 μm in 20-nm CMOS process.
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