L. Kull, Jan Plíva, T. Toifl, M. Schmatz, P. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. Andersen, Y. Leblebici
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引用次数: 19
摘要
提出了一种面积和功率优化的异步32×交错SAR ADC，在110mW下，交错器电源为1V, SAR ADC电源为0.9 V，达到36gs /s。该ADC具有2通道交织器，具有增强带宽的数据解复用功能，具有功率和面积优化的二进制SAR ADC，以及具有可调谐恒流源的面积优化时钟参考缓冲器。采用32nm SOI CMOS技术，在3GHz频率下实现32.6dB SNDR，在18GHz输入频率下实现31.6dB SNDR，实现98fJ/转换步进，核心芯片面积为340×140μm2。
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS
An area- and power-optimized asynchronous 32× interleaved SAR ADC achieving 36 GS/s at 110mW with 1V supply on the interleaver and 0.9 V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a power- and area-optimized binary SAR ADC, and an area-optimized clocked reference buffer with a tunable constant-current source. It achieves 32.6dB SNDR up to 3GHz and 31.6dB up to 18GHz input frequency and 98fJ/conversion-step with a core chip area of 340×140μm2 in 32nm SOI CMOS technology.
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