A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET

Abstract

This paper proposes a low voltage sub-sampling PLL with dynamic threshold MOSFET (DTMOS). DTMOS switch can achieve higher on/off ratio, which prevents signal attenuation and leakage of a sub-sampling phase detector (SSPD) under low supply voltage. The proposed SSPD also employs double-balanced structure to suppress feedthrough in hold mode. DTMOS switches are also applied to a sub-sampling charge pump to reduce undesirable current leak. The proposed PLL was fabricated in a 65nm CMOS. Under the power supply of 0.52V, it shows a in-band phase noise of -98 dBc/Hz at 410 kHz, and the total power consumption of 1.72 mW at 5.71 GHz including frequency-locked loop.