发布求助
文献互助 智能选刊 最新文献

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

筛选
英文 中文
A nonvolatile look-up table using ReRAM for reconfigurable logic 使用ReRAM进行可重构逻辑的非易失性查询表
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008878
Wen-Pin Lin, S. Sheu, Chia-Chen Kuo, P. Tseng, Meng-Fan Chang, K. Su, Chih-Sheng Lin, K. Tsai, Sih-Han Lee, Szu-Chieh Liu, Yu-Sheng Chen, Heng-Yuan Lee, Ching-Chih Hsu, Frederick T. Chen, T. Ku, M. Tsai, M. Kao
{"title":"A nonvolatile look-up table using ReRAM for reconfigurable logic","authors":"Wen-Pin Lin, S. Sheu, Chia-Chen Kuo, P. Tseng, Meng-Fan Chang, K. Su, Chih-Sheng Lin, K. Tsai, Sih-Han Lee, Szu-Chieh Liu, Yu-Sheng Chen, Heng-Yuan Lee, Ching-Chih Hsu, Frederick T. Chen, T. Ku, M. Tsai, M. Kao","doi":"10.1109/ASSCC.2014.7008878","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008878","url":null,"abstract":"This study demonstrated a nonvolatile look-up table (nvLUT) that involves using resistive random access memory (ReRAM) cells with normally-off and instant-on functions for suppressing standby current. Compared with the conventional static random access memory (SRAM)-magnetoresistive random-access memory (MRAM)-hybrid LUTs the proposed ReRAM-based two-input nvLUT circuit decreases the number of transistors and the area of nvLUT by 79% and 90.4%, respectively. The areas of the two- and three-input ReRAM nvLUTs are 11.5% and 74.2% smaller than the other MRAM-based two-input and PCM-based three-input LUTs, respectively. Because of the low current switching and high R-ratio characteristics of ReRAM, the proposed ReRAM-based nvLUT achieves 24% less power consumption than that of SRAM-MRAM-hybrid LUTs. The functionality of the fabricated adder of the three-input ReRAM nvLUT was confirmed using an HfOx-based ReRAM and a 0.18-μm complementary metal-oxide semiconductor with a delay time of 900 ps.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125816034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 0.015-mm2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs 一个0.015-mm2 60ghz可重构唤醒接收器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008890
Rui Wu, Qinghong Bu, W. Deng, K. Okada, A. Matsuzawa
{"title":"A 0.015-mm2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs","authors":"Rui Wu, Qinghong Bu, W. Deng, K. Okada, A. Matsuzawa","doi":"10.1109/ASSCC.2014.7008890","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008890","url":null,"abstract":"An area-efficient 60-GHz wake-up receiver (WuRx) using reconfiguration techniques of multistage low-noise amplifiers (LNAs) is presented. The gain stages of the 60-GHz LNA are reused as the envelope detectors for the wake-up receiver. Therefore, the bulky components such as extra switches between the wake-up receiver and the LNA, additional antennas, and excess input matching network can be removed in the design of the wake-up receiver. Furthermore, due to the reconfigurability of the LNA, the wake-up receiver can work in sensitivity-boost mode by using several LNA gain stages as a pre-amplifier. The wake-up receiver is fabricated in a 65-nm CMOS process occupying a core area of 0.015 mm (excluding the LNA). The WuRx achieves the sensitivity of -46 dBm and -60 dBm with a power consumption of 64 μW and 12.7 mW, respectively.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115198613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
22.5 dB open-loop gain, 31 kHz GBW pseudo-CMOS based operational amplifier with a-IGZO TFTs on a flexible film 22.5 dB开环增益，31 kHz GBW伪cmos运算放大器，柔性薄膜上的a- igzo TFTs
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008923
K. Ishida, R. Shabanpour, B. K. Boroujeni, T. Meister, C. Carta, F. Ellinger, L. Petti, N. Münzenrieder, G. Salvatore, G. Tröster
{"title":"22.5 dB open-loop gain, 31 kHz GBW pseudo-CMOS based operational amplifier with a-IGZO TFTs on a flexible film","authors":"K. Ishida, R. Shabanpour, B. K. Boroujeni, T. Meister, C. Carta, F. Ellinger, L. Petti, N. Münzenrieder, G. Salvatore, G. Tröster","doi":"10.1109/ASSCC.2014.7008923","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008923","url":null,"abstract":"This paper presents an operational amplifier based on pseudo-CMOS blocks and integrated in a flexible a-IGZO TFT technology. The circuit consists of only nMOS transistors, and the pair of active loads is in a pseudo-CMOS configuration. These active loads allow various kinds of common mode feedback schemes or cross-coupled connection, typical for CMOS operational amplifiers. The proposed amplifier is fabricated on a flexible film, and characterized with 5 V supply voltage and an output load capacitance of 15 pF. The measured open-loop gain is 22.5 dB, which is the highest reported for operational amplifiers in metal-oxide TFT technology. The measured bandwidth and gain bandwidth products are 5.6 kHz, and 31 kHz, respectively with 160 μW power consumption, which is lowest among flexible operational amplifies.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114779498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS 一个0.6V 6.4fJ/转换步长10位150MS/s的40nm CMOS分位SAR ADC
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008865
Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen
{"title":"A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS","authors":"Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen","doi":"10.1109/ASSCC.2014.7008865","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008865","url":null,"abstract":"A 0.6V 10-bit 150MS/s single-channel asynchronous subranging SAR ADC using a settling-time relief technique is presented. The technique extends the allocated DAC settling time with the assistance of a coarse ADC and minimizes digital loop delay so that it can reach high speed and low power at a 0.6V supply. This ADC consumes 0.264mW at 150MS/s in 40nm CMOS technology. It achieves an SNDR of 50.5dB at Nyquist rate and results in an FoM of 6.4fJ/c.-s. The core circuit only occupies an area of 0.0063 mm2.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"14 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125887949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 330μW, 64-channel neural recording sensor with embedded spike feature extraction and auto-calibration 一种330μW、64通道神经记录传感器，具有嵌入式尖峰特征提取和自动校准功能
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008896
A. Rodríguez-Pérez, M. Delgado-Restituto, Angela A. Darie, Cristina Soto-Sánchez, Eduardo Fernández-Jover, Ángel Rodríguez-Vázquez
{"title":"A 330μW, 64-channel neural recording sensor with embedded spike feature extraction and auto-calibration","authors":"A. Rodríguez-Pérez, M. Delgado-Restituto, Angela A. Darie, Cristina Soto-Sánchez, Eduardo Fernández-Jover, Ángel Rodríguez-Vázquez","doi":"10.1109/ASSCC.2014.7008896","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008896","url":null,"abstract":"This paper reports an integrated 64-channel neural recording sensor. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by an embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330μW.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128946491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring A 3.3V 15.6b 6.1pJ/0.02%RH, 10ms响应湿度传感器用于呼吸监测
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008918
Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, M. Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee
{"title":"A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring","authors":"Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, M. Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ASSCC.2014.7008918","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008918","url":null,"abstract":"An event-driven and energy-efficient humidity sensor for environment detection and healthcare monitoring is presented. A differential CMOS-MEMS humidity device and proportion-based capacitance-to-digit readout circuit are proposed to overcome PVT variations, and in the meantime to improve sensitivity, response time, and conversion energy. This chip achieves 15.6b 20-90 %RH at 1KS/s, 6.1pJ per 0.02%RH of sensitivity, and 10ms fast response time in TSMC 0.35-μm CMOS MEMS process. With variations in temperature and voltage, our proposal can minimize the errors from 40%RH to 0.2%RH and 50%RH to 0.1%RH, making it very suitable for wearable respiratory monitoring.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125357989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology 基于65nm CMOS技术的50gb /s差分跨阻放大器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008934
Sang Gyun Kim, S. Jung, Y. Eo, S. Kim, Xiao Ying, Hanbyul Choi, Chaerin Hong, Kyungmin Lee, Sung Min Park
{"title":"A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology","authors":"Sang Gyun Kim, S. Jung, Y. Eo, S. Kim, Xiao Ying, Hanbyul Choi, Chaerin Hong, Kyungmin Lee, Sung Min Park","doi":"10.1109/ASSCC.2014.7008934","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008934","url":null,"abstract":"A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm2 including pad.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124086708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET 一种16nm FinFET中3σ误差为+0.64%的超紧凑、无修整CMOS带隙基准
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008886
Chin-Ho Chang, J. Horng, A. Kundu, Chih-Chiang Chang, Y. Peng
{"title":"An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET","authors":"Chin-Ho Chang, J. Horng, A. Kundu, Chih-Chiang Chang, Y. Peng","doi":"10.1109/ASSCC.2014.7008886","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008886","url":null,"abstract":"An ultra-compact sub-1V CMOS bandgap reference circuit is presented. To reduce the chip area the proposed bandgap is realized with 40 stage stack-gate, which adopts a novel layout floorplan without any area penalty. This paper describes two bandgap circuits and are both fabricated in TSMC 16nm FinFET process. The first bandgap aims at applications requiring small-area (area 0.0023 mm2) that achieves medium accuracy (3σVBG 1.67%) without trimming. The second bandgap aims at high-accuracy applications (area 0.013 mm2) that achieve 3σVBG 0.64% without trimming. Both bandgap circuits have good TC performance less than 35ppm/°C between -40°C to 125°C. We claim to have the smallest chip area and highest accuracy when compared to the present state-of-the-art untrimmed CMOS bandgap circuits.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134264827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °C 一种分辨率为0.01°C的CMOS热敏电阻嵌入式连续时间delta-sigma温度传感器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008882
Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin
{"title":"A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °C","authors":"Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2014.7008882","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008882","url":null,"abstract":"A thermistor-embedded continuous-time delta-sigma modulator (CTDSM) implementing a temperature sensor (TS) is proposed in this paper. By embedding the resistor-based temperature sensing module into a 2nd-order 1bit CTDSM, the proposed TS achieves high resolution sensing with reduced hardware complexity and power consumption. Furthermore, a resistor-ladder trimming and compensation scheme is proposed to facilitate the 1-point temperature calibration. The proposed TS is fabricated in a 0.18-μm CMOS process. Over a range of -45 °C ~ 125 °C, this TS achieves 0.01 °C rms temperature resolution with a single conversion time of 100 μs.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123581036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An ultra-low-cost ESD-protected 0.65dB NF +10dBm OP1dB GNSS LNA in 0.18-μm SOI CMOS 基于0.18 μm SOI CMOS的超低成本防静电0.65dB NF +10dBm OP1dB GNSS LNA
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008930
Fei Song, Chun-Geik Tan, O. Shana'a
{"title":"An ultra-low-cost ESD-protected 0.65dB NF +10dBm OP1dB GNSS LNA in 0.18-μm SOI CMOS","authors":"Fei Song, Chun-Geik Tan, O. Shana'a","doi":"10.1109/ASSCC.2014.7008930","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008930","url":null,"abstract":"An ESD-protected GNSS LNA, implemented in 0.18μm SOI CMOS process, uses only one external series inductor as input matching. The input common-source transistor is biased in weak inversion region and operates at Class-AB mode, which greatly improves linearity and saves quiescent current. A bond wire to ground is adopted as source-degeneration and to realize input matching. Design trade-offs among NF, stability and ESD protection are analyzed. The LNA achieves an ultra-low NF of 0.65dB, a power gain of 19.2dB, an output P1dB of +10dBm, while consuming 5.9mA from 2.8V supply. The LNA is housed in a 6-pin LGA package with a die area (including pads) of 0.28mm2. It passes 2.5KV HBM, 200V MM and 250V CDM ESD tests.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124858017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信