一种16nm FinFET中3σ误差为+0.64%的超紧凑、无修整CMOS带隙基准

Chin-Ho Chang, J. Horng, A. Kundu, Chih-Chiang Chang, Y. Peng
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引用次数: 11

摘要

提出了一种超紧凑的sub-1V CMOS带隙参考电路。为了减小芯片面积,该带隙采用40级堆叠栅极实现,该栅极采用了一种新颖的无面积损失的布局方案。本文介绍了两种采用TSMC 16nm FinFET工艺制作的带隙电路。第一个带隙的目标是应用需要小面积(面积0.0023 mm2),达到中等精度(3σVBG 1.67%),而不需要修整。第二个带隙的目标是高精度应用(面积0.013 mm2),达到3σVBG 0.64%而不进行修整。这两种带隙电路在-40°C至125°C之间具有低于35ppm/°C的良好TC性能。与目前最先进的未修剪CMOS带隙电路相比,我们声称具有最小的芯片面积和最高的精度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET
An ultra-compact sub-1V CMOS bandgap reference circuit is presented. To reduce the chip area the proposed bandgap is realized with 40 stage stack-gate, which adopts a novel layout floorplan without any area penalty. This paper describes two bandgap circuits and are both fabricated in TSMC 16nm FinFET process. The first bandgap aims at applications requiring small-area (area 0.0023 mm2) that achieves medium accuracy (3σVBG 1.67%) without trimming. The second bandgap aims at high-accuracy applications (area 0.013 mm2) that achieve 3σVBG 0.64% without trimming. Both bandgap circuits have good TC performance less than 35ppm/°C between -40°C to 125°C. We claim to have the smallest chip area and highest accuracy when compared to the present state-of-the-art untrimmed CMOS bandgap circuits.
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