Chin-Ho Chang, J. Horng, A. Kundu, Chih-Chiang Chang, Y. Peng
{"title":"一种16nm FinFET中3σ误差为+0.64%的超紧凑、无修整CMOS带隙基准","authors":"Chin-Ho Chang, J. Horng, A. Kundu, Chih-Chiang Chang, Y. Peng","doi":"10.1109/ASSCC.2014.7008886","DOIUrl":null,"url":null,"abstract":"An ultra-compact sub-1V CMOS bandgap reference circuit is presented. To reduce the chip area the proposed bandgap is realized with 40 stage stack-gate, which adopts a novel layout floorplan without any area penalty. This paper describes two bandgap circuits and are both fabricated in TSMC 16nm FinFET process. The first bandgap aims at applications requiring small-area (area 0.0023 mm2) that achieves medium accuracy (3σVBG 1.67%) without trimming. The second bandgap aims at high-accuracy applications (area 0.013 mm2) that achieve 3σVBG 0.64% without trimming. Both bandgap circuits have good TC performance less than 35ppm/°C between -40°C to 125°C. We claim to have the smallest chip area and highest accuracy when compared to the present state-of-the-art untrimmed CMOS bandgap circuits.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET\",\"authors\":\"Chin-Ho Chang, J. Horng, A. Kundu, Chih-Chiang Chang, Y. Peng\",\"doi\":\"10.1109/ASSCC.2014.7008886\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An ultra-compact sub-1V CMOS bandgap reference circuit is presented. To reduce the chip area the proposed bandgap is realized with 40 stage stack-gate, which adopts a novel layout floorplan without any area penalty. This paper describes two bandgap circuits and are both fabricated in TSMC 16nm FinFET process. The first bandgap aims at applications requiring small-area (area 0.0023 mm2) that achieves medium accuracy (3σVBG 1.67%) without trimming. The second bandgap aims at high-accuracy applications (area 0.013 mm2) that achieve 3σVBG 0.64% without trimming. Both bandgap circuits have good TC performance less than 35ppm/°C between -40°C to 125°C. We claim to have the smallest chip area and highest accuracy when compared to the present state-of-the-art untrimmed CMOS bandgap circuits.\",\"PeriodicalId\":161031,\"journal\":{\"name\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2014.7008886\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2014.7008886","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET
An ultra-compact sub-1V CMOS bandgap reference circuit is presented. To reduce the chip area the proposed bandgap is realized with 40 stage stack-gate, which adopts a novel layout floorplan without any area penalty. This paper describes two bandgap circuits and are both fabricated in TSMC 16nm FinFET process. The first bandgap aims at applications requiring small-area (area 0.0023 mm2) that achieves medium accuracy (3σVBG 1.67%) without trimming. The second bandgap aims at high-accuracy applications (area 0.013 mm2) that achieve 3σVBG 0.64% without trimming. Both bandgap circuits have good TC performance less than 35ppm/°C between -40°C to 125°C. We claim to have the smallest chip area and highest accuracy when compared to the present state-of-the-art untrimmed CMOS bandgap circuits.