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2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel 16.8Gbps/通道单端收发器，65nm CMOS，用于硅载波通道上基于SiP的DRAM接口
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008876
Hyunbae Lee, Taeksang Song, Sangyeon Byeon, Kwanghun Lee, I. Jung, Seongjin Kang, O. Kwon, Koeun Cheon, Donghwan Seol, Jong Kang, Gunwoo Park, Yunsaing Kim
{"title":"A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel","authors":"Hyunbae Lee, Taeksang Song, Sangyeon Byeon, Kwanghun Lee, I. Jung, Seongjin Kang, O. Kwon, Koeun Cheon, Donghwan Seol, Jong Kang, Gunwoo Park, Yunsaing Kim","doi":"10.1109/ASSCC.2014.7008876","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008876","url":null,"abstract":"A 16.8Gbps/channel single ended transceiver for SiP based DRAM interface on silicon carrier channel is presented. A transmitter, receiver, and channel are all included in a single package. On the transmitter, 1 tap FFEs are used in 4:1 MUX and in output driver. On the receiver, source follower based CTLEs and self Vref generator are used for obtaining effective single ended signaling on Si-carrier channel. A BER that is less than 1e-12 is achieved in 65nm CMOS. The power efficiency of the transceiver is 5.9pJ/bit with 120Ω terminations at each transceiver side.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125211669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An area-efficient capacitively-coupled instrumentation amplifier with a duty-cycled Gm-C DC servo loop in 0.18-μm CMOS 一种面积高效电容耦合仪器放大器，在0.18 μm CMOS中具有占空比Gm-C直流伺服回路
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008883
Chih-Chan Tu, Feng-Wen Lee, Tsung-Hsien Lin
{"title":"An area-efficient capacitively-coupled instrumentation amplifier with a duty-cycled Gm-C DC servo loop in 0.18-μm CMOS","authors":"Chih-Chan Tu, Feng-Wen Lee, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2014.7008883","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008883","url":null,"abstract":"A chopped capacitively-coupled instrumentation amplifier (CCIA) with a proposed duty-cycled Gm-C DC servo loop (DSL) for bio-potential signal acquisition is presented. The proposed architecture realizes a large time constant with small circuit area without sacrificing noise and power performance. Furthermore, this pseudo-resistor-less design grants this architecture easily portable for more advanced processes. Fabricated in a 0.18-μm CMOS, this chip draws 2.37 μA from a 1.8-V supply and occupies only an active area of 0.43 mm2. The total integrated noise from 0.5 to 100 Hz is 1.04 μVrms and results in a noise efficiency factor of 7.8.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116680951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor 一种间歇性驱动的供电电流均衡器，可在抗cpa的128位AES加密处理器中节省11倍和4倍的功耗开销
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008901
N. Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, M. Nagata
{"title":"An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor","authors":"N. Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, M. Nagata","doi":"10.1109/ASSCC.2014.7008901","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008901","url":null,"abstract":"A supply-current equalizer disables a Correlation Power Analysis (CPA) attack on an AES cryptographic processor. An intermittent equalizer operation only at processing rounds critical to key disclosure suppresses the equalizer power overhead significantly. For this low-power intermittent operation, a Thru operation mode is proposed with minimum hardware overhead. A level-shift comparator hides its own power consumption in an internal equalized virtual supply to guarantee secure protection of a secret key. Test-chip measurement in 0.18μm CMOS successfully demonstrates CPA-attack resiliency. For the key protection against mostly-common last-round CPA, the equalizer power overhead is reduced by 11x which is only 8% of 128bit AES processor power consumption, and by 4x even including the initial/1st-rounds CPA protection capability.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126737736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication 一种140万像素CMOS图像传感器，具有基于多行重新扫描的数据采样，用于光学相机通信
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008849
J. Deguchi, Toshiyuki Yamagishi, H. Majima, Nau Ozaki, Kazuhiro Hiwada, Makoto Morimoto, T. Ashitani, S. Kousai
{"title":"A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication","authors":"J. Deguchi, Toshiyuki Yamagishi, H. Majima, Nau Ozaki, Kazuhiro Hiwada, Makoto Morimoto, T. Ashitani, S. Kousai","doi":"10.1109/ASSCC.2014.7008849","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008849","url":null,"abstract":"A 1.4Mpixel CMOS image sensor (CIS) with multiple row-rescan (MRR) based data sampling for optical camera communication (OCC) is presented. The CIS achieves a data sampling rate at a row-scan rate of 51kS/s even with a frame rate of 30fps, a pixel size of 2.2mm × 2.2mm by multiply rescanning the rows at a modulated LED spot. The detectable minimum LED size projected onto the CIS becomes 13.2mm × 13.2mm. The MRR could be a practical solution for IEEE 802.15.SG7a OCC.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128390177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of −40 to 170°C with test screening against write disturb issues 40 nm双端口和双端口sram，适用于- 40至170°C的宽温度范围内的汽车MCU应用，具有针对写入干扰问题的测试筛选
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008851
Yoshisato Yokoyama, Y. Ishii, Koji Tanaka, T. Fukuda, Y. Tsujihashi, A. Miyanishi, S. Asayama, K. Maekawa, K. Shiba, K. Nii
{"title":"40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of −40 to 170°C with test screening against write disturb issues","authors":"Yoshisato Yokoyama, Y. Ishii, Koji Tanaka, T. Fukuda, Y. Tsujihashi, A. Miyanishi, S. Asayama, K. Maekawa, K. Shiba, K. Nii","doi":"10.1109/ASSCC.2014.7008851","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008851","url":null,"abstract":"A 2-read/write dual-port SRAM and 1-read/1-write two-port SRAM with stable operation at temperatures of -40 to 170°C are implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. To reduce the leakage current and to ensure the read/write operating margin at over 125°C, a new 8T SRAM bitcell with the optimized process and sizing is proposed. A test circuit for screening disturb failures for dual-port and two-port SRAMs is also proposed. Designed and fabricated test chips showed that measured Vmin is achieved under 0.7 V with good distribution. Results show that the proposed test circuits can screen the disturb failures effectively.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121395732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Ultra-low voltage datapath blocks in 28nm UTBB FD-SOI 超低电压数据通路模块采用28nm UTBB FD-SOI
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008857
Hans Reyserhove, N. Reynders, W. Dehaene
{"title":"Ultra-low voltage datapath blocks in 28nm UTBB FD-SOI","authors":"Hans Reyserhove, N. Reynders, W. Dehaene","doi":"10.1109/ASSCC.2014.7008857","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008857","url":null,"abstract":"This paper demonstrates a wide supply range multiply-accumulate datapath block in 28nm UTBB FD-SOI technology. Variability and leakage reduction strategies are employed in this new technology to achieve a state-of-the-art low energy performance. The design uses a wide range of supply voltages to reduce energy consumption per operation. The extensive back-gate biasing range allows to adapt the minimum energy point (MEP) of the circuit to the desired workload. Measurements showcase the speed/energy trade-off of both the design and the technology and lead to a MEP of 0.17pJ at 35MHz with a supply voltage of 250mV and a back-gate bias of 0.5V.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114357090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement 1V输入，3- 6v输出，集成了58%效率的电荷泵，混合拓扑和寄生能量收集，面积减少66%，效率提高11%
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008903
Jen-Huan Tsai, Sheng-An Ko, Hui-Huan Wang, Chia-Wei Wang, Hsin Chen, Po-Chiun Huang
{"title":"A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement","authors":"Jen-Huan Tsai, Sheng-An Ko, Hui-Huan Wang, Chia-Wei Wang, Hsin Chen, Po-Chiun Huang","doi":"10.1109/ASSCC.2014.7008903","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008903","url":null,"abstract":"This paper presents a low-area, high-efficiency hybrid 6-stage voltage multiplier by cascoding Dickson chargepumps and modified Cockcroft-Walton charge-pumps, and paralleling them with auxiliary charge-pumps. The proposed architecture obtains a good area and efficiency performance without using high-V devices or external capacitors. Implemented in a standard 0.18-μm CMOS process, the prototype provides a wide output range of 3-6V and 30-240μA load from a 1-V supply with an efficiency of 48-58% (52% at 6V). By using on-chip MOS capacitors as internal pumping capacitors, a 66% area reduction is gained. The area shrinks to 0.05mm2 per 9× interleaved cell. The efficiency loss due to parasitics is compensated by creating auxiliary parasitic pumping paths to collect parasitic energy. With this feed-forward charge-pump, the efficiency increases extra 11%. Higher efficiency is thus measured than most reported on-chip Dickson CPs and cascoded doublers of comparable gain.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"55 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131776547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 103 pJ/bit multi-channel reconfigurable GMSK/PSK/16-QAM transmitter with band-shaping 一个103 pJ/bit多通道可重构GMSK/PSK/16-QAM带带整形发射机
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008912
Xiayun Liu, Teng Kok Hin, C. Heng, Yuan Gao, Wei-Da Toh, San-Jeow Cheng, M. Je
{"title":"A 103 pJ/bit multi-channel reconfigurable GMSK/PSK/16-QAM transmitter with band-shaping","authors":"Xiayun Liu, Teng Kok Hin, C. Heng, Yuan Gao, Wei-Da Toh, San-Jeow Cheng, M. Je","doi":"10.1109/ASSCC.2014.7008912","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008912","url":null,"abstract":"A 401~406MHz GMSK/PSK/16-QAM TX with band-shaping is realized in 65nm CMOS occupying area of 0.4mm2. Coupled DLL based phase interpolated synthesizer with injection-locked ring oscillator, we achieve frequency tuning and multi-phase output without any need of phase calibration. Through direct quadrature modulation at digital PA, the TX achieves less than 6% EVM for data rate up to 12.5Mb/s. The band-shaping maximizes spectral efficiency with ACPR of -33dB. Consuming 2.57mW, the TX achieves energy efficiency of 103pJ/bit.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"12390 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130239606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor 用于移动增强现实处理器的27mW可重构无标记对数相机姿态估计引擎
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008897
Injoon Hong, Gyeonghoon Kim, Youchang Kim, Donghyun Kim, Byeong-Gyu Nam, H. Yoo
{"title":"A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor","authors":"Injoon Hong, Gyeonghoon Kim, Youchang Kim, Donghyun Kim, Byeong-Gyu Nam, H. Yoo","doi":"10.1109/ASSCC.2014.7008897","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008897","url":null,"abstract":"A marker-less Camera Pose Estimation Engine (CPEE) with reconfigurable logarithmic processor is proposed for the view angle estimation in the low-power mobile Augmented Reality (AR) applications. The proposed CPEE is required to overcome 150x huge gap in computational cost for marker-less pose estimation including floating-point operations resulting in the bottlenecks in mobile platforms. Speculative Execution (SE) and Reconfigurable Data-arrangement Layer (RDL) are proposed to reduce the computing time of CPEE by 17% and 27%, respectively. For low-power implementation of floating-point units, Logarithmic Processing Element (LPE) is used to reduce overall power consumption by 18% with maximum conversion error under 0.49%. The proposed marker-less CPEE is fabricated in 65nm Logic CMOS technology, and successfully realizes real-time marker-less camera pose estimation with only 27mW power consumption.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116185859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit 一个6gb /s自适应环路带宽时钟和数据恢复(CDR)电路
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008917
Li-Hung Chiueh, Tai-Cheng Lee
{"title":"A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit","authors":"Li-Hung Chiueh, Tai-Cheng Lee","doi":"10.1109/ASSCC.2014.7008917","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008917","url":null,"abstract":"An adaptive circuit is proposed to adjust CDR loop bandwidth based on different jitter spectral profile for better jitter performance. The preventional lock detector (PLD) is employed to achieve better jitter suppression ability without jitter tolerance (JTOL) degradation. The proposed circuit enhances the jitter suppression by 14.14 dB at an 8-MHz sinusoidal jitter source. This adaptive block is fully-digital synthesized and the whole circuit consumes 86.4 mW for a 6-Gb/s input data.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121224401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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